Patchwork [1/6] tcg: Document double-word support opcodes.

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Submitter Richard Henderson
Date Jan. 7, 2010, 6:07 p.m.
Message ID <21946e7af50464b232e601fbad0bea0e288be04f.1264007896.git.rth@twiddle.net>
Download mbox | patch
Permalink /patch/43320/
State New
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Comments

Richard Henderson - Jan. 7, 2010, 6:07 p.m.
The internal opcodes brcond2, add2, sub2, mulu2 were undocumented.
Place these in a new section that clearly indicates that they are
not to be emitted by translators.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/README |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)

Patch

diff --git a/tcg/README b/tcg/README
index e672258..3d6c170 100644
--- a/tcg/README
+++ b/tcg/README
@@ -323,6 +323,29 @@  st32_i64 t0, t1, offset
 write(t0, t1 + offset)
 Write 8, 16, 32 or 64 bits to host memory.
 
+********* 64-bit target on 32-bit host support
+
+The following opcodes are internal to TCG.  Thus they are to be implemented by
+32-bit host code generators, but are not to be emitted by guest translators.
+They are emitted as needed by inline functions within "tcg-op.h".
+
+* brcond2_i32 cond, t0_low, t0_high, t1_low, t1_high, label
+
+Similar to brcond, except that the 64-bit values T0 and T1
+are formed from two 32-bit arguments.
+
+* add2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
+* sub2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
+
+Similar to add/sub, except that the 64-bit inputs T1 and T2 are
+formed from two 32-bit arguments, and the 64-bit output T0
+is returned in two 32-bit outputs.
+
+* mulu2_i32 t0_low, t0_high, t1, t2
+
+Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding
+the full 64-bit product T0.  The later is returned in two 32-bit outputs.
+
 ********* QEMU specific operations
 
 * tb_exit t0