| Message ID | 1421954574-5160-1-git-send-email-ehabkost@redhat.com |
|---|---|
| State | New |
| Headers | show |
On 22/01/2015 20:22, Eduardo Habkost wrote: > All Haswell CPUs and some Broadwell CPUs were updated by Intel to have > the HLE and RTM features disabled. This will prevent > "-cpu Haswell,enforce" and "-cpu Broadwell,enforce" from running out of > the box on those CPUs. > > Disable those features by default on Broadwell and Haswell CPU models, > starting on pc-*-2.3. Users who want to use those features can enable > them explicitly on the command-line. > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Applied. My offer to add yourself to MAINTAINERS for target-i386/ is still valid. :) Paolo > --- > hw/i386/pc_piix.c | 4 ++++ > hw/i386/pc_q35.c | 4 ++++ > target-i386/cpu.c | 9 ++++----- > 3 files changed, 12 insertions(+), 5 deletions(-) > > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index f0a3201..a475b33 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -328,6 +328,10 @@ static void pc_compat_2_2(MachineState *machine) > x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); > x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C); > x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); > + x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX, > + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); > + x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX, > + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); > } > > static void pc_compat_2_1(MachineState *machine) > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > index a432944..63027ee 100644 > --- a/hw/i386/pc_q35.c > +++ b/hw/i386/pc_q35.c > @@ -307,6 +307,10 @@ static void pc_compat_2_2(MachineState *machine) > x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); > x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C); > x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); > + x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX, > + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); > + x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX, > + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); > } > > static void pc_compat_2_1(MachineState *machine) > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index b81ac5c..3a9b32e 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -1100,9 +1100,8 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_EXT3_LAHF_LM, > .features[FEAT_7_0_EBX] = > CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | > - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > - CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | > - CPUID_7_0_EBX_RTM, > + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID, > .features[FEAT_XSAVE] = > CPUID_XSAVE_XSAVEOPT, > .xlevel = 0x8000000A, > @@ -1135,9 +1134,9 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, > .features[FEAT_7_0_EBX] = > CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | > - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | > - CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | > + CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | > CPUID_7_0_EBX_SMAP, > .features[FEAT_XSAVE] = > CPUID_XSAVE_XSAVEOPT, >
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f0a3201..a475b33 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -328,6 +328,10 @@ static void pc_compat_2_2(MachineState *machine) x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); + x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX, + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); + x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX, + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); } static void pc_compat_2_1(MachineState *machine) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a432944..63027ee 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -307,6 +307,10 @@ static void pc_compat_2_2(MachineState *machine) x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); + x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX, + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); + x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX, + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); } static void pc_compat_2_1(MachineState *machine) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index b81ac5c..3a9b32e 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1100,9 +1100,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_7_0_EBX] = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | - CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | - CPUID_7_0_EBX_RTM, + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, .xlevel = 0x8000000A, @@ -1135,9 +1134,9 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, .features[FEAT_7_0_EBX] = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | - CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT,
All Haswell CPUs and some Broadwell CPUs were updated by Intel to have the HLE and RTM features disabled. This will prevent "-cpu Haswell,enforce" and "-cpu Broadwell,enforce" from running out of the box on those CPUs. Disable those features by default on Broadwell and Haswell CPU models, starting on pc-*-2.3. Users who want to use those features can enable them explicitly on the command-line. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- hw/i386/pc_piix.c | 4 ++++ hw/i386/pc_q35.c | 4 ++++ target-i386/cpu.c | 9 ++++----- 3 files changed, 12 insertions(+), 5 deletions(-)