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[2/4] target-tricore: Add instructions of RR2 opcode format

Message ID 1421863489-7716-3-git-send-email-kbastian@mail.uni-paderborn.de
State New
Headers show

Commit Message

Bastian Koppelmann Jan. 21, 2015, 6:04 p.m. UTC 
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

Comments

Richard Henderson Jan. 21, 2015, 6:16 p.m. UTC | #1 
On 01/21/2015 10:04 AM, Bastian Koppelmann wrote:
> +    case OPC2_32_RR2_MUL_32:
> +        gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
> +        break;
> +    case OPC2_32_RR2_MUL_64:
> +        gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
> +                     cpu_gpr_d[r2]);
> +        break;

What happend to flags computation?


r~
Bastian Koppelmann Jan. 22, 2015, 2:58 p.m. UTC | #2 
On 01/21/2015 06:16 PM, Richard Henderson wrote:
> On 01/21/2015 10:04 AM, Bastian Koppelmann wrote:
>> +    case OPC2_32_RR2_MUL_32:
>> +        gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
>> +        break;
>> +    case OPC2_32_RR2_MUL_64:
>> +        gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
>> +                     cpu_gpr_d[r2]);
>> +        break;
> What happend to flags computation?
If you are talking about the PSW flags, they are computed in their 
respective functions: gen_mul_i32s and
gen_mul_i64s.

Cheers,
Bastian
>
> r~
diff mbox

Patch

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index da8ecbc..4af31c2 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -5051,6 +5051,39 @@  static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx)
     tcg_temp_free(temp2);
 }
 
+/* RR2 format */
+static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
+{
+    uint32_t op2;
+    int r1, r2, r3;
+
+    op2 = MASK_OP_RR2_OP2(ctx->opcode);
+    r1  = MASK_OP_RR2_S1(ctx->opcode);
+    r2  = MASK_OP_RR2_S2(ctx->opcode);
+    r3  = MASK_OP_RR2_D(ctx->opcode);
+    switch (op2) {
+    case OPC2_32_RR2_MUL_32:
+        gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+        break;
+    case OPC2_32_RR2_MUL_64:
+        gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
+                     cpu_gpr_d[r2]);
+        break;
+    case OPC2_32_RR2_MULS_32:
+        gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+                            cpu_gpr_d[r2]);
+        break;
+    case OPC2_32_RR2_MUL_U_64:
+        gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
+                     cpu_gpr_d[r2]);
+        break;
+    case OPC2_32_RR2_MULS_U_32:
+        gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+                            cpu_gpr_d[r2]);
+        break;
+    }
+}
+
 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
 {
     int op1;
@@ -5311,6 +5344,10 @@  static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
     case OPCM_32_RR1_MULQ:
         decode_rr1_mulq(env, ctx);
         break;
+/* RR2 format */
+    case OPCM_32_RR2_MUL:
+        decode_rr2_mul(env, ctx);
+        break;
     }
 }