| Message ID | 1421745476-6276-2-git-send-email-svarbanov@mm-sol.com |
|---|---|
| State | New |
| Headers | show |
On Tue 20 Jan 01:17 PST 2015, Stanimir Varbanov wrote: > From: Joonwoo Park <joonwoop@codeaurora.org> > > Newer MSM SoCs have TLMM hardware block upper than 16 bit. Increase to > 32 bit registers to hold addresses correctly. > It's not the addresses but rather the offsets and the reason is that the registers are now spread so we need offsets >16 bit to address them. And this is to be able to benefit from page based access control. Could you please update the subject and commit message to be slightly more accurate? > Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> > Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> > --- > drivers/pinctrl/qcom/pinctrl-msm.h | 10 +++++----- > 1 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h > index b952c4b..54fdd04 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.h > +++ b/drivers/pinctrl/qcom/pinctrl-msm.h > @@ -70,11 +70,11 @@ struct msm_pingroup { > unsigned *funcs; > unsigned nfuncs; > > - s16 ctl_reg; > - s16 io_reg; > - s16 intr_cfg_reg; > - s16 intr_status_reg; > - s16 intr_target_reg; > + u32 ctl_reg; > + u32 io_reg; > + u32 intr_cfg_reg; > + u32 intr_status_reg; > + u32 intr_target_reg; > > unsigned mux_bit:5; > The patch itself looks good! Regards, Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index b952c4b..54fdd04 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -70,11 +70,11 @@ struct msm_pingroup { unsigned *funcs; unsigned nfuncs; - s16 ctl_reg; - s16 io_reg; - s16 intr_cfg_reg; - s16 intr_status_reg; - s16 intr_target_reg; + u32 ctl_reg; + u32 io_reg; + u32 intr_cfg_reg; + u32 intr_status_reg; + u32 intr_target_reg; unsigned mux_bit:5;