[SH] Introduce treg_set_expr

Hi,

The attached patch does a couple of things, which are based on the
treg_set_expr (for an explanation/motivation see below).  Somehow the
stuff just kept piling on and it was difficult to make step-by-step
patches for all the individual issues.  Some patterns needed to be
rewritten to keep the existing test cases happy.  Some patterns became
redundant.  If really really needed, I could try to split it into
multiple patches that do the changes bit by bit.  However, it makes only
sense as a whole somehow.

Tested with
make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"

and one new failure on SH2A (-m2a):
FAIL: tr1/6_containers/unordered_set/26132.cc execution test

which is a heap-stack collision.  Since that test case has been failing
here before for the other SH variants in the same way, I didn't pursue
it further.

There is one minor fallout/regression that this patch causes, which is
reduced usage of the SH2A movu.{b|w} insn (zero extending QI/HImode mem
load).  I had to disable the expansion of that insn as it makes
eliminating zero extensions a bit difficult in some cases.  The movu.{b|
w} insn should be used as a last-resort option in a peephole like pass
after combine/split1, but before RA.  I'll try to fix that soon.

Kaz, could you please test the patch on your sh4-linux setup and report
your findings?  Even though it's a bit late, I'd like to get this in for
GCC 5, if it doesn't break too many things.

Cheers,
Oleg

treg_set_expr explanation/motivation:

On SH there are insns that compute a value and store the result in the T
bit (1 bit register), such as comparison results, shifted out MSB/LSB
bits etc.  Then there are also insns which take the T bit as an operand,
such as rotates or add/sub/neg-with-carry.  Some of the insns that set
the T bit are only discovered during combine.  div0s is one such
example:

(define_insn "cmp_div0s"
  [(set (reg:SI T_REG)
	(lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
			     (match_operand:SI 1 "arith_reg_operand" "r"))
		     (const_int 31)))]
  "TARGET_SH1"
  "div0s	%0,%1"
  [(set_attr "type" "arith")])

In order to match e.g. div0s-addc or div0s-subc sequences, it's usually
required to write down patterns for all the combinations.  Instead of
doing that, I had the idea of a special operand predicate which would
match any expression for which there is an insn in the .md that does
   (set (reg:SI T_REG) (<expr>))

This predicate then can be used in insns that take the T bit as an
operand like this:

(define_insn_and_split "*addc"
  [(set (match_operand:SI 0 "arith_reg_dest")
	(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
			  (match_operand:SI 2 "arith_reg_or_0_operand"))
		 (match_operand 3 "treg_set_expr")))
   (clobber (reg:SI T_REG))]

... which means for operand 3: Match any expression, which can be
calculated into the T bit, using one of the existing patterns in
the .md.  After combine, in the split1 pass, a function is used to split
out the appropriate T bit setting insn and substitute the expression at
operand 3 with a simple T_REG.

This makes the example addc pattern above automatically cover cases such
as reg+reg+1, reg+reg+(reg & 1), reg+reg+((reg >> 31) & 1), since there
are insns that can do T = 1, T = reg & 1, T = (reg >> 31) & 1.

Then there are also some insns (again discovered during combine) which
can only store the result into the T bit, such as the single bit extract
patterns.  However, if those results are required in a GP reg instead of
the T bit, it's usually required to add insn_and_split variants that do
a T -> GP reg move afterwards.
The treg_set_expr predicate can be used to match all those insns with a
single one:
(define_insn_and_split "any_treg_expr_to_reg"
  [(set (match_operand:SI 0 "arith_reg_dest")
	(match_operand 1 "treg_set_expr"))
   (clobber (reg:SI T_REG))]

... which then splits out the appropriate T bit setting insn and appends
a T -> GP reg move.

Having the treg_set_expr thing opens some new doors here and there to
implement specific insn (re-)combinations, which combine would not
handle that easily by itself.  For example, some of the single bit zero
extracts can store only the negated extracted bit in the T bit register.
When this is fed into an addc insn, the explicit T bit negation can be
avoided by replacing the addc insn with a subc insn.

The whole thing is implemented by constructing a temporary insn
   (set (reg:SI T_REG) (<expr>))
and invoking recog.  However, since this happens while matching the
treg_set_expr predicate, recog must be invoked in a re-entrant way.  To
do that, the global recog_data struct needs to be saved and restored
before returning back into recog.  This seems to work OK.  If any other
target is interested in doing the same, maybe we should extend recog
itself and make it re-entrant.

gcc/ChangeLog
	PR target/49263
	PR target/53987
	PR target/64345
	PR target/59533
	PR target/52933
	PR target/54236
	PR target/51244

	* config/sh/sh-protos.h
	(sh_extending_set_of_reg::can_use_as_unextended_reg,
	sh_extending_set_of_reg::use_as_unextended_reg,
	sh_is_nott_insn, sh_movt_set_dest, sh_movrt_set_dest, sh_is_movt_insn,
	sh_is_movrt_insn, sh_insn_operands_modified_between_p,
	sh_reg_dead_or_unused_after_insn, sh_in_recog_treg_set_expr,
	sh_recog_treg_set_expr, sh_split_treg_set_expr): New functions.
	(sh_treg_insns): New class.

	* config/sh/sh.c (TARGET_LEGITIMATE_COMBINED_INSN): Define target hook.
	(scope_counter): New class.
	(sh_legitimate_combined_insn, sh_is_nott_insn, sh_movt_set_dest,
	sh_movrt_set_dest, sh_reg_dead_or_unused_after_insn,
	sh_extending_set_of_reg::can_use_as_unextended_reg,
	sh_extending_set_of_reg::use_as_unextended_reg, sh_recog_treg_set_expr,
	sh_in_recog_treg_set_expr, sh_try_split_insn_simple,
	sh_split_treg_set_expr): New functions.
	(addsubcosts): Handle treg_set_expr.
	(sh_rtx_costs): Handle IF_THEN_ELSE and ZERO_EXTRACT.
	(sh_rtx_costs): Use arith_reg_operand in SIGN_EXTEND and ZERO_EXTEND.
	(sh_rtx_costs): Handle additional bit test patterns in EQ and AND cases.
	(sh_insn_operands_modified_between_p): Make non-static.

	* config/sh/predicates.md (zero_extend_movu_operand): Allow
	simple_mem_operand in addition to displacement_mem_operand.
	(zero_extend_operand): Don't allow zero_extend_movu_operand.
	(treg_set_expr, treg_set_expr_not_const01,
	arith_reg_or_treg_set_expr): New predicates.

	* config/sh/sh.md (tstsi_t): Use arith_reg_operand and
	arith_or_int_operand instead of logical_operand.  Convert to
	insn_and_split.  Try to optimize constant operand in splitter.
	(tsthi_t, tstqi_t): Fold into *tst<mode>_t.  Convert to insn_and_split.
	(*tstqi_t_zero): Delete.
	(*tst<mode>_t_subregs): Add !sh_in_recog_treg_set_expr split condition.
	(tstsi_t_and_not): Delete.
	(tst<mode>_t_zero_extract_eq): Rename to *tst<mode>_t_zero_extract.
	Convert to insn_and_split.
	(unnamed split, tstsi_t_zero_extract_xor,
	tstsi_t_zero_extract_subreg_xor_little,
	tstsi_t_zero_extract_subreg_xor_big): Delete.
	(*tstsi_t_shift_mask): New insn_and_split.
	(cmpeqsi_t, cmpgesi_t): Add new split for const_int 0 operands and try
	to recombine with surrounding insns when splitting.
	(*negtstsi): Add !sh_in_recog_treg_set_expr condition.
	(cmp_div0s_0, cmp_div0s_1, *cmp_div0s_0, *cmp_div0s_1): Rewrite as ...
	(cmp_div0s, *cmp_div0s_1, *cmp_div0s_2, *cmp_div0s_3, *cmp_div0s_4,
	*cmp_div0s_5, *cmp_div0s_6): ... these new insn_and_split patterns.
	(*cbranch_div0s: Delete.
	(*addc): Convert to insn_and_split.  Use treg_set_expr as 3rd operand.
	Try to recombine with surrounding insns when splitting.  Add operand
	order variants.
	(*addc_t_r, *addc_r_t): Use treg_set_expr_not_const01.
	(*addc_r_r_1, *addc_r_lsb, *addc_r_r_lsb, *addc_r_lsb_r, *addc_r_msb,
	*addc_r_r_msb, *addc_2r_msb): Delete.
	(*addc_2r_lsb): Rename to *addc_2r_t.  Use treg_set_expr.  Add operand
	order variant.
	(*addc_negreg_t): New insn_and_split.
	(*subc): Convert to insn_and_split.  Use treg_set_expr as 3rd operand.
	Try to recombine with surrounding insns when splitting.
	Add operand order variants.  
	(*subc_negt_reg, *subc_negreg_t, *reg_lsb_t, *reg_msb_t): New
	insn_and_split patterns.
	(*rotcr): Use arith_reg_or_treg_set_expr.  Try to recombine with
	surrounding insns when splitting.
	(unnamed rotcr split): Use arith_reg_or_treg_set_expr.
	(*rotcl): Likewise.  Add zero_extract variant.
	(*ashrsi2_31): New insn_and_split.
	(*negc): Convert to insn_and_split.  Use treg_set_expr.
	(*zero_extend<mode>si2_disp_mem): Update comment.
	(movrt_negc, *movrt_negc, nott): Add !sh_in_recog_treg_set_expr split
	condition.
	(*mov_t_msb_neg, mov_neg_si_t): Use treg_set_expr.  Try to recombine
	with surrounding insns when splitting.
	(any_treg_expr_to_reg): New insn_and_split.
	(*neg_zero_extract_0, *neg_zero_extract_1, *neg_zero_extract_2,
	*neg_zero_extract_3, *neg_zero_extract_4, *neg_zero_extract_5,
	*neg_zero_extract_6, *zero_extract_0, *zero_extract_1,
	*zero_extract_2): New single bit zero extract patterns.
	(bld_reg, *bld_regqi): Fold into bld<mode>_reg.

gcc/testsuite/ChangeLog:
	PR target/49263
	PR target/53987
	PR target/64345
	PR target/59533
	PR target/52933
	PR target/54236
	PR target/51244
	* gcc.target/sh/pr64345-1.c: New.
	* gcc.target/sh/pr64345-2.c: New.
	* gcc.target/sh/pr59533-1.c: New.
	* gcc.target/sh/pr49263.c: Adjust matching of expected insns.
	* gcc.target/sh/pr52933-2.c: Likewise.
	* gcc.target/sh/pr54089-1.c: Likewise.
	* gcc.target/sh/pr54236-1.c: Likewise.
	* gcc.target/sh/pr51244-20-sh2a.c: Likewise.
	* gcc.target/sh/pr49263-1.c: Remove xfails.
	* gcc.target/sh/pr49263-2.c: Likewise.
	* gcc.target/sh/pr49263-3.c: Likewise.
	* gcc.target/sh/pr53987-1.c: Likewise.
	* gcc.target/sh/pr52933-1.c: Adjust matching of expected insns.
	(test_24, test_25, test_26, test_27, test_28, test_29, test_30): New.
	* gcc.target/sh/pr51244-12.c: Adjust matching of expected insns.
	(test05, test06, test07, test08, test09, test10, test11, test12): New.
	* gcc.target/sh/pr54236-3.c: Adjust matching of expected insns.
	(test_002, test_003, test_004, test_005, test_006, test_007, test_008,
	test_009): New.
	* gcc.target/sh/pr51244-4.c: Adjust matching of expected insns.
	(test_02): New.

[SH] Introduce treg_set_expr

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