diff mbox

[2/5] powerpc/head fsl: move the temp 4KiB mapping to TLB0

Message ID 1263573697-17839-3-git-send-email-linuxppc-dev@ml.breakpoint.cc (mailing list archive)
State Superseded
Delegated to: Kumar Gala
Headers show

Commit Message

Sebastian Andrzej Siewior Jan. 15, 2010, 4:41 p.m. UTC
From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

Right now the setup code takes ESEL of the current mapping and puts the
temporary into ESEL (old_ESEL & 1 ) + 1 which is either one or two.
This is actually not required since all slots in TLB0 are invalid by now
and can be used.
This patch moved the temp mapping to TLB0, ESEL[0]. The invalidation of
TLB0 does not care about IPPROT so that part can go as well.
The benefit is that now the setup code may set every slot of TLB1 while
before that it was not allowed to touch ESEL one or two depending on the
old_ESEL.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/powerpc/kernel/head_fsl_booke.S |   20 +++++---------------
 1 files changed, 5 insertions(+), 15 deletions(-)

Comments

Kumar Gala Feb. 18, 2010, 3:09 a.m. UTC | #1
On Jan 15, 2010, at 10:41 AM, Sebastian Andrzej Siewior wrote:

> From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> 
> Right now the setup code takes ESEL of the current mapping and puts the
> temporary into ESEL (old_ESEL & 1 ) + 1 which is either one or two.
> This is actually not required since all slots in TLB0 are invalid by now
> and can be used.
> This patch moved the temp mapping to TLB0, ESEL[0]. The invalidation of
> TLB0 does not care about IPPROT so that part can go as well.
> The benefit is that now the setup code may set every slot of TLB1 while
> before that it was not allowed to touch ESEL one or two depending on the
> old_ESEL.
> 
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> ---
> arch/powerpc/kernel/head_fsl_booke.S |   20 +++++---------------
> 1 files changed, 5 insertions(+), 15 deletions(-)

this is problematic, we can't assume that TLB0 is safe.  It possible some other software is running on a second core and does a broadcast tlbivax which will wipe what's in TLB0.

- k
Sebastian Andrzej Siewior Feb. 18, 2010, 9:08 a.m. UTC | #2
* Kumar Gala | 2010-02-17 21:09:08 [-0600]:

>
>On Jan 15, 2010, at 10:41 AM, Sebastian Andrzej Siewior wrote:
>
>> From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
>> 
>> Right now the setup code takes ESEL of the current mapping and puts the
>> temporary into ESEL (old_ESEL & 1 ) + 1 which is either one or two.
>> This is actually not required since all slots in TLB0 are invalid by now
>> and can be used.
>> This patch moved the temp mapping to TLB0, ESEL[0]. The invalidation of
>> TLB0 does not care about IPPROT so that part can go as well.
>> The benefit is that now the setup code may set every slot of TLB1 while
>> before that it was not allowed to touch ESEL one or two depending on the
>> old_ESEL.
>> 
>> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
>> ---
>> arch/powerpc/kernel/head_fsl_booke.S |   20 +++++---------------
>> 1 files changed, 5 insertions(+), 15 deletions(-)
>
>this is problematic, we can't assume that TLB0 is safe.  It possible some other software is running on a second core and does a broadcast tlbivax which will wipe what's in TLB0.

Ah right SMP. So if CPU0 would wait until CPU1-X are up and kick them
one by one could make it work but is not that pretty.
So let me think of something. I will probably just skip the current
mapping while making new ones for kexec.

>- k

Sebastian
diff mbox

Patch

diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 799ddbe..cc76952 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -165,8 +165,6 @@  skpinv:	addi	r6,r6,1				/* Increment */
 	TLBSYNC
 
 /* 3. Setup a temp mapping and jump to it */
-	andi.	r5, r3, 0x1	/* Find an entry not used and is non-zero */
-	addi	r5, r5, 0x1
 	lis	r7,0x1000	/* Set MAS0(TLBSEL) = 1 */
 	rlwimi	r7,r3,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r3) */
 	mtspr	SPRN_MAS0,r7
@@ -194,12 +192,11 @@  skpinv:	addi	r6,r6,1				/* Increment */
 	ori	r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
 
 	/* Just modify the entry ID and EPN for the temp mapping */
-	lis	r7,0x1000	/* Set MAS0(TLBSEL) = 1 */
-	rlwimi	r7,r5,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r5) */
+	li	r7, 0		/* Set MAS0(TLBSEL) = 0 | ESEL(0) */
 	mtspr	SPRN_MAS0,r7
 	xori	r6,r4,1		/* Setup TMP mapping in the other Address space */
 	slwi	r6,r6,12
-	oris	r6,r6,(MAS1_VALID|MAS1_IPROT)@h
+	oris	r6,r6,(MAS1_VALID)@h
 	ori	r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
 	mtspr	SPRN_MAS1,r6
 	mfspr	r6,SPRN_MAS2
@@ -281,16 +278,9 @@  skpinv:	addi	r6,r6,1				/* Increment */
 	rfi				/* start execution out of TLB1[0] entry */
 
 /* 8. Clear out the temp mapping */
-2:	lis	r7,0x1000	/* Set MAS0(TLBSEL) = 1 */
-	rlwimi	r7,r5,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r5) */
-	mtspr	SPRN_MAS0,r7
-	tlbre
-	mfspr	r8,SPRN_MAS1
-	rlwinm	r8,r8,0,2,0	/* clear IPROT */
-	mtspr	SPRN_MAS1,r8
-	tlbwe
-	/* Invalidate TLB1 */
-	li	r9,0x0c
+2:
+	/* Invalidate TLB0 */
+	li	r9,0x04
 	tlbivax 0,r9
 	TLBSYNC