@@ -1768,7 +1768,7 @@ unsigned long get_arm_clk(void)
unsigned long get_i2c_clk(void)
{
if (cpu_is_exynos5()) {
- return exynos5_get_i2c_clk();
+ return clock_get_periph_rate(PERIPH_ID_I2C0);
} else if (cpu_is_exynos4()) {
return exynos4_get_i2c_clk();
} else {
@@ -1780,8 +1780,6 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
} else {
if (proid_is_exynos4412())
@@ -1792,10 +1790,28 @@ unsigned long get_pwm_clk(void)
unsigned long get_uart_clk(int dev_index)
{
+ enum periph_id id;
+
+ switch (dev_index) {
+ case 0:
+ id = PERIPH_ID_UART0;
+ break;
+ case 1:
+ id = PERIPH_ID_UART1;
+ break;
+ case 2:
+ id = PERIPH_ID_UART2;
+ break;
+ case 3:
+ id = PERIPH_ID_UART3;
+ break;
+ default:
+ debug("%s: invalid UART index %d", __func__, dev_index);
+ return -1;
+ }
+
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_uart_clk(dev_index);
- return exynos5_get_uart_clk(dev_index);
+ return clock_get_periph_rate(id);
} else {
if (proid_is_exynos4412())
return exynos4x12_get_uart_clk(dev_index);
@@ -1805,10 +1821,28 @@ unsigned long get_uart_clk(int dev_index)
unsigned long get_mmc_clk(int dev_index)
{
+ enum periph_id id;
+
+ switch (dev_index) {
+ case 0:
+ id = PERIPH_ID_SDMMC0;
+ break;
+ case 1:
+ id = PERIPH_ID_SDMMC1;
+ break;
+ case 2:
+ id = PERIPH_ID_SDMMC2;
+ break;
+ case 3:
+ id = PERIPH_ID_SDMMC3;
+ break;
+ default:
+ debug("%s: invalid MMC index %d", __func__, dev_index);
+ return -1;
+ }
+
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_mmc_clk(dev_index);
- return exynos5_get_mmc_clk(dev_index);
+ return clock_get_periph_rate(id);
} else {
return exynos4_get_mmc_clk(dev_index);
}
Replacing SoC and peripheral specific function calls with generic clock_get_periph_rate calls to get the peripheral clocks. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> --- Changes since v2: - No change. Changes since v1: - Separated exynos5_get_periph_rate fixes into another patch. arch/arm/cpu/armv7/exynos/clock.c | 52 ++++++++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 9 deletions(-)