| Message ID | 1421329328-18070-1-git-send-email-akshay.s@samsung.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Minkyu Kang |
| Headers | show |
On 15/01/15 22:41, Akshay Saraswat wrote: > This patch adds code to shutdown secondary cores. > When U-boot comes up, all secondary cores appear powered on, > which is undesirable and causes side effects while > initializing these cores in kernel. > > Secondary core power down happens in following steps: > > Step-1: After Exynos power-on, primary core starts executing first. > Step-2: In iROM code every core has to check 2 flags i.e. > addresses 0x02020028 & 0x02020004. > Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a > jump address for primary core and 0 for all secondary cores. > Step-4: Therefore, primary core follows normal iROM execution and jumps > to BL1 eventually, whereas all secondary cores enter WFE. > Step-5: When primary core comes into function secondary_cores_configure, > it puts pointer to function power_down_core into 0x02020004 > and provides DSB and SEV for all cores so that they may come out > of WFE and jump to power_down_core function. > Step-6: And ultimately because of power_down_core all > secondary cores shut-down. > > Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> > Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> > --- > arch/arm/cpu/armv7/exynos/lowlevel_init.c | 62 ++++++++++++++++++++++ > arch/arm/include/asm/arch-exynos/cpu.h | 30 +++++++++++ > arch/arm/include/asm/arch-exynos/system.h | 87 +++++++++++++++++++++++++++++++ > 3 files changed, 179 insertions(+) > > diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c > index 83e1dcf..43c957b 100644 > --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c > +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c > @@ -31,6 +31,7 @@ > #include <asm/arch/tzpc.h> > #include <asm/arch/periph.h> > #include <asm/arch/pinmux.h> > +#include <asm/arch/system.h> > #include "common_setup.h" > > /* These are the things we can do during low-level init */ > @@ -42,6 +43,62 @@ enum { > DO_POWER = 1 << 4, > }; > > +#ifdef CONFIG_EXYNOS5420 > +/* > + * Pointer to this function is stored in iRam which is used > + * for jump and power down of a specific core. > + */ > +static void power_down_core(void) > +{ > + uint32_t tmp, core_id, core_config; > + > + /* Get the core id */ > + mrc_mpafr(core_id); > + tmp = core_id & 0x3; > + core_id = (core_id >> 6) & ~3; Please explain what means each bits. > + core_id |= tmp; > + > + /* Set the status of the core to low */ > + core_config = (core_id * CORE_CONFIG_OFFSET); > + core_config += ARM_CORE0_CONFIG; > + writel(0x0, core_config); > + > + /* Core enter WFI */ > + wfi(); > +} > + > +/* > + * Configurations for secondary cores are inapt at this stage. > + * Reconfigure secondary cores. Shutdown and change the status > + * of all cores except the primary core. > + */ > +static void secondary_cores_configure(void) > +{ > + uint32_t core_id; > + > + /* Store jump address for power down of secondary cores */ > + writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4); > + > + /* Need all core power down check */ > + dsb(); > + sev(); > + > + /* > + * Power down all cores(secondary) while primary core must > + * wait for all cores to go down. > + */ > + for (core_id = 1; core_id != CORE_COUNT; core_id++) { > + while ((readl(ARM_CORE0_STATUS > + + (core_id * CORE_CONFIG_OFFSET)) > + & 0xff) != 0x0) { > + isb(); > + sev(); > + } > + isb(); > + } > +} > +#endif > + > int do_lowlevel_init(void) > { > uint32_t reset_status; > @@ -49,6 +106,11 @@ int do_lowlevel_init(void) > > arch_cpu_init(); > > +#ifdef CONFIG_EXYNOS5420 > + /* Reconfigure secondary cores */ > + secondary_cores_configure(); > +#endif > + > reset_status = get_reset_status(); > > switch (reset_status) { > diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h > index 29674ad..f1f9994 100644 > --- a/arch/arm/include/asm/arch-exynos/cpu.h > +++ b/arch/arm/include/asm/arch-exynos/cpu.h > @@ -177,6 +177,7 @@ > #define EXYNOS5420_GPIO_PART1_BASE 0x14010000 > #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 > #define EXYNOS5420_DP_BASE 0x145B0000 > +#define EXYNOS5420_INF_REG_BASE 0x10040800 > > #define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE > #define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE > @@ -186,6 +187,35 @@ > #define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE > #define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE > > +#define ARM_CORE0_CONFIG (EXYNOS5420_POWER_BASE + 0x2000) > +#define ARM_CORE0_STATUS (EXYNOS5420_POWER_BASE + 0x2004) > +#define CORE_CONFIG_OFFSET 0x80 > +#define CORE_COUNT 0x8 are they for all exynos SoCs? > + > +/* > + * POWER > + */ for power then it should be gone into power.h > +#define PMU_BASE EXYNOS5420_POWER_BASE > +#define SW_RST_REG_OFFSET 0x400 > + > +#define INF_REG_BASE EXYNOS5420_INF_REG_BASE > +#define INF_REG0_OFFSET 0x00 > +#define INF_REG1_OFFSET 0x04 > +#define INF_REG2_OFFSET 0x08 > +#define INF_REG3_OFFSET 0x0C > +#define INF_REG4_OFFSET 0x10 > +#define INF_REG5_OFFSET 0x14 > +#define INF_REG6_OFFSET 0x18 > +#define INF_REG7_OFFSET 0x1C > + > +#define PMU_SPARE_BASE (EXYNOS5420_INF_REG_BASE + 0x100) > +#define PMU_SPARE_0 PMU_SPARE_BASE > +#define PMU_SPARE_1 (PMU_SPARE_BASE + 0x4) > +#define PMU_SPARE_2 (PMU_SPARE_BASE + 0x8) > +#define PMU_SPARE_3 (PMU_SPARE_BASE + 0xc) We do NOT allow such an accessor. > +#define RST_FLAG_REG PMU_SPARE_BASE > +#define RST_FLAG_VAL 0xfcba0d10 > + > #ifndef __ASSEMBLY__ > #include <asm/io.h> > /* CPU detection macros */ Thanks, Minkyu Kang.
Hi, On 15 January 2015 at 23:35, Minkyu Kang <mk7.kang@samsung.com> wrote: > On 15/01/15 22:41, Akshay Saraswat wrote: >> This patch adds code to shutdown secondary cores. >> When U-boot comes up, all secondary cores appear powered on, >> which is undesirable and causes side effects while >> initializing these cores in kernel. >> >> Secondary core power down happens in following steps: >> >> Step-1: After Exynos power-on, primary core starts executing first. >> Step-2: In iROM code every core has to check 2 flags i.e. >> addresses 0x02020028 & 0x02020004. >> Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a >> jump address for primary core and 0 for all secondary cores. >> Step-4: Therefore, primary core follows normal iROM execution and jumps >> to BL1 eventually, whereas all secondary cores enter WFE. >> Step-5: When primary core comes into function secondary_cores_configure, >> it puts pointer to function power_down_core into 0x02020004 >> and provides DSB and SEV for all cores so that they may come out >> of WFE and jump to power_down_core function. >> Step-6: And ultimately because of power_down_core all >> secondary cores shut-down. >> >> Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> >> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> >> --- >> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 62 ++++++++++++++++++++++ >> arch/arm/include/asm/arch-exynos/cpu.h | 30 +++++++++++ >> arch/arm/include/asm/arch-exynos/system.h | 87 +++++++++++++++++++++++++++++++ >> 3 files changed, 179 insertions(+) >> >> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c >> index 83e1dcf..43c957b 100644 >> --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c >> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c >> @@ -31,6 +31,7 @@ >> #include <asm/arch/tzpc.h> >> #include <asm/arch/periph.h> >> #include <asm/arch/pinmux.h> >> +#include <asm/arch/system.h> >> #include "common_setup.h" >> >> /* These are the things we can do during low-level init */ >> @@ -42,6 +43,62 @@ enum { >> DO_POWER = 1 << 4, >> }; >> >> +#ifdef CONFIG_EXYNOS5420 >> +/* >> + * Pointer to this function is stored in iRam which is used >> + * for jump and power down of a specific core. >> + */ >> +static void power_down_core(void) >> +{ >> + uint32_t tmp, core_id, core_config; >> + >> + /* Get the core id */ >> + mrc_mpafr(core_id); >> + tmp = core_id & 0x3; >> + core_id = (core_id >> 6) & ~3; > > Please explain what means each bits. > >> + core_id |= tmp; >> + >> + /* Set the status of the core to low */ >> + core_config = (core_id * CORE_CONFIG_OFFSET); >> + core_config += ARM_CORE0_CONFIG; >> + writel(0x0, core_config); >> + >> + /* Core enter WFI */ >> + wfi(); >> +} >> + >> +/* >> + * Configurations for secondary cores are inapt at this stage. >> + * Reconfigure secondary cores. Shutdown and change the status >> + * of all cores except the primary core. >> + */ >> +static void secondary_cores_configure(void) >> +{ >> + uint32_t core_id; >> + >> + /* Store jump address for power down of secondary cores */ >> + writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4); >> + >> + /* Need all core power down check */ >> + dsb(); >> + sev(); >> + >> + /* >> + * Power down all cores(secondary) while primary core must >> + * wait for all cores to go down. >> + */ >> + for (core_id = 1; core_id != CORE_COUNT; core_id++) { >> + while ((readl(ARM_CORE0_STATUS >> + + (core_id * CORE_CONFIG_OFFSET)) >> + & 0xff) != 0x0) { >> + isb(); >> + sev(); >> + } >> + isb(); >> + } >> +} >> +#endif >> + >> int do_lowlevel_init(void) >> { >> uint32_t reset_status; >> @@ -49,6 +106,11 @@ int do_lowlevel_init(void) >> >> arch_cpu_init(); >> >> +#ifdef CONFIG_EXYNOS5420 >> + /* Reconfigure secondary cores */ >> + secondary_cores_configure(); >> +#endif >> + >> reset_status = get_reset_status(); >> >> switch (reset_status) { >> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h >> index 29674ad..f1f9994 100644 >> --- a/arch/arm/include/asm/arch-exynos/cpu.h >> +++ b/arch/arm/include/asm/arch-exynos/cpu.h >> @@ -177,6 +177,7 @@ >> #define EXYNOS5420_GPIO_PART1_BASE 0x14010000 >> #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 >> #define EXYNOS5420_DP_BASE 0x145B0000 >> +#define EXYNOS5420_INF_REG_BASE 0x10040800 >> >> #define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE >> #define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE >> @@ -186,6 +187,35 @@ >> #define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE >> #define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE >> >> +#define ARM_CORE0_CONFIG (EXYNOS5420_POWER_BASE + 0x2000) >> +#define ARM_CORE0_STATUS (EXYNOS5420_POWER_BASE + 0x2004) >> +#define CORE_CONFIG_OFFSET 0x80 >> +#define CORE_COUNT 0x8 > > are they for all exynos SoCs? > >> + >> +/* >> + * POWER >> + */ > > for power then it should be gone into power.h > >> +#define PMU_BASE EXYNOS5420_POWER_BASE >> +#define SW_RST_REG_OFFSET 0x400 >> + >> +#define INF_REG_BASE EXYNOS5420_INF_REG_BASE >> +#define INF_REG0_OFFSET 0x00 >> +#define INF_REG1_OFFSET 0x04 >> +#define INF_REG2_OFFSET 0x08 >> +#define INF_REG3_OFFSET 0x0C >> +#define INF_REG4_OFFSET 0x10 >> +#define INF_REG5_OFFSET 0x14 >> +#define INF_REG6_OFFSET 0x18 >> +#define INF_REG7_OFFSET 0x1C >> + >> +#define PMU_SPARE_BASE (EXYNOS5420_INF_REG_BASE + 0x100) >> +#define PMU_SPARE_0 PMU_SPARE_BASE >> +#define PMU_SPARE_1 (PMU_SPARE_BASE + 0x4) >> +#define PMU_SPARE_2 (PMU_SPARE_BASE + 0x8) >> +#define PMU_SPARE_3 (PMU_SPARE_BASE + 0xc) > > We do NOT allow such an accessor. > Are these actually used? Maybe just remove them? >> +#define RST_FLAG_REG PMU_SPARE_BASE >> +#define RST_FLAG_VAL 0xfcba0d10 >> + >> #ifndef __ASSEMBLY__ >> #include <asm/io.h> >> /* CPU detection macros */ > > Thanks, > Minkyu Kang. > Tested on snow, pit, pi Tested-by: Simon Glass <sjg@chromium.org> Regards, Simon
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c index 83e1dcf..43c957b 100644 --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c @@ -31,6 +31,7 @@ #include <asm/arch/tzpc.h> #include <asm/arch/periph.h> #include <asm/arch/pinmux.h> +#include <asm/arch/system.h> #include "common_setup.h" /* These are the things we can do during low-level init */ @@ -42,6 +43,62 @@ enum { DO_POWER = 1 << 4, }; +#ifdef CONFIG_EXYNOS5420 +/* + * Pointer to this function is stored in iRam which is used + * for jump and power down of a specific core. + */ +static void power_down_core(void) +{ + uint32_t tmp, core_id, core_config; + + /* Get the core id */ + mrc_mpafr(core_id); + tmp = core_id & 0x3; + core_id = (core_id >> 6) & ~3; + core_id |= tmp; + + /* Set the status of the core to low */ + core_config = (core_id * CORE_CONFIG_OFFSET); + core_config += ARM_CORE0_CONFIG; + writel(0x0, core_config); + + /* Core enter WFI */ + wfi(); +} + +/* + * Configurations for secondary cores are inapt at this stage. + * Reconfigure secondary cores. Shutdown and change the status + * of all cores except the primary core. + */ +static void secondary_cores_configure(void) +{ + uint32_t core_id; + + /* Store jump address for power down of secondary cores */ + writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4); + + /* Need all core power down check */ + dsb(); + sev(); + + /* + * Power down all cores(secondary) while primary core must + * wait for all cores to go down. + */ + for (core_id = 1; core_id != CORE_COUNT; core_id++) { + while ((readl(ARM_CORE0_STATUS + + (core_id * CORE_CONFIG_OFFSET)) + & 0xff) != 0x0) { + isb(); + sev(); + } + isb(); + } +} +#endif + int do_lowlevel_init(void) { uint32_t reset_status; @@ -49,6 +106,11 @@ int do_lowlevel_init(void) arch_cpu_init(); +#ifdef CONFIG_EXYNOS5420 + /* Reconfigure secondary cores */ + secondary_cores_configure(); +#endif + reset_status = get_reset_status(); switch (reset_status) { diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 29674ad..f1f9994 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -177,6 +177,7 @@ #define EXYNOS5420_GPIO_PART1_BASE 0x14010000 #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 #define EXYNOS5420_DP_BASE 0x145B0000 +#define EXYNOS5420_INF_REG_BASE 0x10040800 #define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE @@ -186,6 +187,35 @@ #define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE +#define ARM_CORE0_CONFIG (EXYNOS5420_POWER_BASE + 0x2000) +#define ARM_CORE0_STATUS (EXYNOS5420_POWER_BASE + 0x2004) +#define CORE_CONFIG_OFFSET 0x80 +#define CORE_COUNT 0x8 + +/* + * POWER + */ +#define PMU_BASE EXYNOS5420_POWER_BASE +#define SW_RST_REG_OFFSET 0x400 + +#define INF_REG_BASE EXYNOS5420_INF_REG_BASE +#define INF_REG0_OFFSET 0x00 +#define INF_REG1_OFFSET 0x04 +#define INF_REG2_OFFSET 0x08 +#define INF_REG3_OFFSET 0x0C +#define INF_REG4_OFFSET 0x10 +#define INF_REG5_OFFSET 0x14 +#define INF_REG6_OFFSET 0x18 +#define INF_REG7_OFFSET 0x1C + +#define PMU_SPARE_BASE (EXYNOS5420_INF_REG_BASE + 0x100) +#define PMU_SPARE_0 PMU_SPARE_BASE +#define PMU_SPARE_1 (PMU_SPARE_BASE + 0x4) +#define PMU_SPARE_2 (PMU_SPARE_BASE + 0x8) +#define PMU_SPARE_3 (PMU_SPARE_BASE + 0xc) +#define RST_FLAG_REG PMU_SPARE_BASE +#define RST_FLAG_VAL 0xfcba0d10 + #ifndef __ASSEMBLY__ #include <asm/io.h> /* CPU detection macros */ diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h index 4968d3d..86903c3 100644 --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -37,6 +37,93 @@ struct exynos5_sysreg { #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) +#ifdef CONFIG_EXYNOS5420 +/* + * Data Synchronization Barrier acts as a special kind of memory barrier. + * No instruction in program order after this instruction executes until + * this instruction completes. This instruction completes when: + * - All explicit memory accesses before this instruction complete. + * - All Cache, Branch predictor and TLB maintenance operations before + * this instruction complete. + */ +#define dsb() __asm__ __volatile__ ("dsb\n\t" : : ); + +/* + * This instruction causes an event to be signaled to all cores + * within a multiprocessor system. If SEV is implemented, + * WFE must also be implemented. + */ +#define sev() __asm__ __volatile__ ("sev\n\t" : : ); +/* + * If the Event Register is not set, WFE suspends execution until + * one of the following events occurs: + * - an IRQ interrupt, unless masked by the CPSR I-bit + * - an FIQ interrupt, unless masked by the CPSR F-bit + * - an Imprecise Data abort, unless masked by the CPSR A-bit + * - a Debug Entry request, if Debug is enabled + * - an Event signaled by another processor using the SEV instruction. + * If the Event Register is set, WFE clears it and returns immediately. + * If WFE is implemented, SEV must also be implemented. + */ +#define wfe() __asm__ __volatile__ ("wfe\n\t" : : ); + +/* Move 0xd3 value to CPSR register to enable SVC mode */ +#define svc32_mode_en() __asm__ __volatile__ \ + ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ + "msr cpsr_c, #0x13|0xC0\n\t" : : ) + +/* Set program counter with the given value */ +#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) + +/* Read Main Id register */ +#define mrc_midr(x) __asm__ __volatile__ \ + ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : ) + +/* Read Multiprocessor Affinity Register */ +#define mrc_mpafr(x) __asm__ __volatile__ \ + ("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : ) + +/* Read System Control Register */ +#define mrc_sctlr(x) __asm__ __volatile__ \ + ("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : ) + +/* Read Auxiliary Control Register */ +#define mrc_auxr(x) __asm__ __volatile__ \ + ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : ) + +/* Read L2 Control register */ +#define mrc_l2_ctlr(x) __asm__ __volatile__ \ + ("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : ) + +/* Read L2 Auxilliary Control register */ +#define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \ + ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : ) + +/* Write System Control Register */ +#define mcr_sctlr(x) __asm__ __volatile__ \ + ("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x)) + +/* Write Auxiliary Control Register */ +#define mcr_auxr(x) __asm__ __volatile__ \ + ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x)) + +/* Invalidate all instruction caches to PoU */ +#define mcr_icache(x) __asm__ __volatile__ \ + ("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x)) + +/* Invalidate unified TLB */ +#define mcr_tlb(x) __asm__ __volatile__ \ + ("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x)) + +/* Write L2 Control register */ +#define mcr_l2_ctlr(x) __asm__ __volatile__ \ + ("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x)) + +/* Write L2 Auxilliary Control register */ +#define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \ + ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x)) +#endif + void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); int exynos_lcd_early_init(const void *blob);