Documentation: gpio: fix bindings document
diff mbox

Message ID 1421311960-4120-1-git-send-email-yamada.m@jp.panasonic.com
State New, archived
Headers show

Commit Message

Masahiro Yamada Jan. 15, 2015, 8:52 a.m. UTC
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 Documentation/devicetree/bindings/gpio/gpio.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Laurent Pinchart Jan. 15, 2015, 2 p.m. UTC | #1
Hi Yamada-san,

Thank you for the patch.

On Thursday 15 January 2015 17:52:40 Masahiro Yamada wrote:
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> 
>  Documentation/devicetree/bindings/gpio/gpio.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt
> b/Documentation/devicetree/bindings/gpio/gpio.txt index b9bd1d6..f7a158d
> 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio.txt
> @@ -69,7 +69,8 @@ GPIO pin number, and GPIO flags as accepted by the
> "qe_pio_e" gpio-controller. ----------------------------------
> 
>  A gpio-specifier should contain a flag indicating the GPIO polarity;
> active- -high or active-low. If it does, the follow best practices should
> be followed: +high or active-low. If it does, the following best practices
> should be +followed:
> 
>  The gpio-specifier's polarity flag should represent the physical level at
> the GPIO controller that achieves (or represents, for inputs) a logically
> asserted @@ -147,7 +148,7 @@ contains information structures as follows:
>  	numeric-gpio-range ::=
>  			<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
>  	named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
> -	gpio-phandle : phandle to pin controller node.
> +	pinctrl-phandle : phandle to pin controller node
>  	gpio-base : Base GPIO ID in the GPIO controller
>  	pinctrl-base : Base pinctrl pin ID in the pin controller
>  	count : The number of GPIOs/pins in this range
Rob Herring Jan. 15, 2015, 2:07 p.m. UTC | #2
On Thu, Jan 15, 2015 at 2:52 AM, Masahiro Yamada
<yamada.m@jp.panasonic.com> wrote:
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Perhaps some explanation. You can't just remove properties. Please
explain to what extent the old/wrong name is used. This patch is only
okay if there are no users of gpio-phandle.

Rob

> ---
>
>  Documentation/devicetree/bindings/gpio/gpio.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
> index b9bd1d6..f7a158d 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio.txt
> @@ -69,7 +69,8 @@ GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
>  ----------------------------------
>
>  A gpio-specifier should contain a flag indicating the GPIO polarity; active-
> -high or active-low. If it does, the follow best practices should be followed:
> +high or active-low. If it does, the following best practices should be
> +followed:
>
>  The gpio-specifier's polarity flag should represent the physical level at the
>  GPIO controller that achieves (or represents, for inputs) a logically asserted
> @@ -147,7 +148,7 @@ contains information structures as follows:
>         numeric-gpio-range ::=
>                         <pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
>         named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
> -       gpio-phandle : phandle to pin controller node.
> +       pinctrl-phandle : phandle to pin controller node
>         gpio-base : Base GPIO ID in the GPIO controller
>         pinctrl-base : Base pinctrl pin ID in the pin controller
>         count : The number of GPIOs/pins in this range
> --
> 1.9.1
>
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Laurent Pinchart Jan. 15, 2015, 2:10 p.m. UTC | #3
Hi Rob,

On Thursday 15 January 2015 08:07:18 Rob Herring wrote:
> On Thu, Jan 15, 2015 at 2:52 AM, Masahiro Yamada
> 
> <yamada.m@jp.panasonic.com> wrote:
> > Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> 
> Perhaps some explanation. You can't just remove properties. Please
> explain to what extent the old/wrong name is used. This patch is only
> okay if there are no users of gpio-phandle.

As far as I understand the patch just fixes a typo. There has never been a 
gpio-phandle for GPIO controllers, only for GPIO consumers.

> > ---
> > 
> >  Documentation/devicetree/bindings/gpio/gpio.txt | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt
> > b/Documentation/devicetree/bindings/gpio/gpio.txt index b9bd1d6..f7a158d
> > 100644
> > --- a/Documentation/devicetree/bindings/gpio/gpio.txt
> > +++ b/Documentation/devicetree/bindings/gpio/gpio.txt
> > @@ -69,7 +69,8 @@ GPIO pin number, and GPIO flags as accepted by the
> > "qe_pio_e" gpio-controller.> 
> >  ----------------------------------
> >  
> >  A gpio-specifier should contain a flag indicating the GPIO polarity;
> >  active-> 
> > -high or active-low. If it does, the follow best practices should be
> > followed: +high or active-low. If it does, the following best practices
> > should be> 
> > +followed:
> >  The gpio-specifier's polarity flag should represent the physical level at
> >  the GPIO controller that achieves (or represents, for inputs) a
> >  logically asserted> 
> > @@ -147,7 +148,7 @@ contains information structures as follows:
> >         numeric-gpio-range ::=
> >         
> >                         <pinctrl-phandle> <gpio-base> <pinctrl-base>
> >                         <count>
> >         
> >         named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
> > 
> > -       gpio-phandle : phandle to pin controller node.
> > +       pinctrl-phandle : phandle to pin controller node
> > 
> >         gpio-base : Base GPIO ID in the GPIO controller
> >         pinctrl-base : Base pinctrl pin ID in the pin controller
> >         count : The number of GPIOs/pins in this range
Masahiro Yamada Jan. 16, 2015, 1:20 a.m. UTC | #4
Hi Laurent, Rob,


On Thu, 15 Jan 2015 16:10:54 +0200
Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote:

> Hi Rob,
> 
> On Thursday 15 January 2015 08:07:18 Rob Herring wrote:
> > On Thu, Jan 15, 2015 at 2:52 AM, Masahiro Yamada
> > 
> > <yamada.m@jp.panasonic.com> wrote:
> > > Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> > 
> > Perhaps some explanation. You can't just remove properties. Please
> > explain to what extent the old/wrong name is used. This patch is only
> > okay if there are no users of gpio-phandle.
> 
> As far as I understand the patch just fixes a typo. There has never been a 
> gpio-phandle for GPIO controllers, only for GPIO consumers.


Yes, this patch just fixes typos.
I thought I could be lazy here...



> > > ---
> > > 
> > >  Documentation/devicetree/bindings/gpio/gpio.txt | 5 +++--
> > >  1 file changed, 3 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt
> > > b/Documentation/devicetree/bindings/gpio/gpio.txt index b9bd1d6..f7a158d
> > > 100644
> > > --- a/Documentation/devicetree/bindings/gpio/gpio.txt
> > > +++ b/Documentation/devicetree/bindings/gpio/gpio.txt
> > > @@ -69,7 +69,8 @@ GPIO pin number, and GPIO flags as accepted by the
> > > "qe_pio_e" gpio-controller.> 
> > >  ----------------------------------
> > >  
> > >  A gpio-specifier should contain a flag indicating the GPIO polarity;
> > >  active-> 
> > > -high or active-low. If it does, the follow best practices should be
> > > followed: +high or active-low. If it does, the following best practices
> > > should be> 
> > > +followed:
> > >  The gpio-specifier's polarity flag should represent the physical level at
> > >  the GPIO controller that achieves (or represents, for inputs) a
> > >  logically asserted> 
> > > @@ -147,7 +148,7 @@ contains information structures as follows:
> > >         numeric-gpio-range ::=
> > >         
> > >                         <pinctrl-phandle> <gpio-base> <pinctrl-base>
> > >                         <count>
> > >         
> > >         named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
> > > 
> > > -       gpio-phandle : phandle to pin controller node.
> > > +       pinctrl-phandle : phandle to pin controller node
> > > 
> > >         gpio-base : Base GPIO ID in the GPIO controller
> > >         pinctrl-base : Base pinctrl pin ID in the pin controller
> > >         count : The number of GPIOs/pins in this range
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 
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Linus Walleij Jan. 19, 2015, 10:34 a.m. UTC | #5
On Thu, Jan 15, 2015 at 9:52 AM, Masahiro Yamada
<yamada.m@jp.panasonic.com> wrote:

> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Patch applied with Laurent's ACK.

Yours,
Linus Walleij
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Patch
diff mbox

diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index b9bd1d6..f7a158d 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -69,7 +69,8 @@  GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
 ----------------------------------
 
 A gpio-specifier should contain a flag indicating the GPIO polarity; active-
-high or active-low. If it does, the follow best practices should be followed:
+high or active-low. If it does, the following best practices should be
+followed:
 
 The gpio-specifier's polarity flag should represent the physical level at the
 GPIO controller that achieves (or represents, for inputs) a logically asserted
@@ -147,7 +148,7 @@  contains information structures as follows:
 	numeric-gpio-range ::=
 			<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
 	named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
-	gpio-phandle : phandle to pin controller node.
+	pinctrl-phandle : phandle to pin controller node
 	gpio-base : Base GPIO ID in the GPIO controller
 	pinctrl-base : Base pinctrl pin ID in the pin controller
 	count : The number of GPIOs/pins in this range