@@ -97,6 +97,7 @@
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_FSL_ERRATUM_A008378
#else
#error SoC not defined
#endif
@@ -171,6 +171,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
ddr_out32(&ddr->debug[i], regs->debug[i]);
}
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
+ /* Erratum applies when accumulated ECC is used, or DBI is enabled */
+#define IS_ACC_ECC_EN(v) ((v) & 0x4)
+#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
+ if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
+ IS_DBI(regs->ddr_sdram_cfg_3))
+ ddr_setbits32(ddr->debug[28], 0x9 << 20);
+#endif
/*
* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
@@ -23,9 +23,15 @@
#ifdef CONFIG_SYS_FSL_DDR_LE
#define ddr_in32(a) in_le32(a)
#define ddr_out32(a, v) out_le32(a, v)
+#define ddr_setbits32(a, v) setbits_le32(a, v)
+#define ddr_clrbits32(a, v) clrbits_le32(a, v)
+#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
#else
#define ddr_in32(a) in_be32(a)
#define ddr_out32(a, v) out_be32(a, v)
+#define ddr_setbits32(a, v) setbits_be32(a, v)
+#define ddr_clrbits32(a, v) clrbits_be32(a, v)
+#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
#endif
#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
Internal memory controller counters can reach a bad state after training in DDR4 mode if accumulated ECC or DBI mode is eanbled. Signed-off-by: York Sun <yorksun@freescale.com> --- Change log v2: Add access macros to handle big- and little-endian. These macros were added by other patches, but not yet merged. Add parentheses for logic in macro, as suggested by compiling warning arch/arm/include/asm/arch-ls102xa/config.h | 1 + drivers/ddr/fsl/fsl_ddr_gen4.c | 8 ++++++++ include/fsl_ddr.h | 6 ++++++ 3 files changed, 15 insertions(+)