diff mbox

[U-Boot,PATCHv1,06/22] arm: socfpga: add functions to bring sdram, timer, and uart out of reset

Message ID 1421253662-27222-7-git-send-email-dinguyen@opensource.altera.com
State Superseded
Delegated to: Marek Vasut
Headers show

Commit Message

Dinh Nguyen Jan. 14, 2015, 4:40 p.m. UTC 
From: Dinh Nguyen <dinguyen@opensource.altera.com>

These functions will be needed for use by the SPL for enabling the
console and sdram initialization.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/cpu/armv7/socfpga/reset_manager.c        | 24 +++++++++++++++++++++++
 arch/arm/include/asm/arch-socfpga/reset_manager.h |  6 ++++++
 2 files changed, 30 insertions(+)

Comments

Marek Vasut Jan. 14, 2015, 11:42 p.m. UTC | #1 
On Wednesday, January 14, 2015 at 05:40:46 PM, dinguyen@opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> These functions will be needed for use by the SPL for enabling the
> console and sdram initialization.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut
Pavel Machek Jan. 16, 2015, 7:06 p.m. UTC | #2 
On Wed 2015-01-14 10:40:46, dinguyen@opensource.altera.com wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> These functions will be needed for use by the SPL for enabling the
> console and sdram initialization.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Acked-by: Pavel Machek <pavel@denx.de>
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index 25921e7..45b352b 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -113,3 +113,27 @@  void socfpga_spim_enable(void)
 	clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
 		     (1 << RSTMGR_PERMODRST_SPIM1_LSB));
 }
+
+/* Bring UART0 out of reset. */
+void socfpga_uart0_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB);
+}
+
+/* Bring SDRAM controller out of reset. */
+void socfpga_sdram_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB);
+}
+
+/* Bring OSC1 timer out of reset. */
+void socfpga_osc1timer_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB);
+}
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 034135b..d63a285 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -15,6 +15,9 @@  void socfpga_bridges_reset(int enable);
 void socfpga_emac_reset(int enable);
 void socfpga_watchdog_reset(void);
 void socfpga_spim_enable(void);
+void socfpga_uart0_enable(void);
+void socfpga_sdram_enable(void);
+void socfpga_osc1timer_enable(void);
 
 struct socfpga_reset_manager {
 	u32	status;
@@ -36,7 +39,10 @@  struct socfpga_reset_manager {
 #define RSTMGR_PERMODRST_EMAC0_LSB	0
 #define RSTMGR_PERMODRST_EMAC1_LSB	1
 #define RSTMGR_PERMODRST_L4WD0_LSB	6
+#define RSTMGR_PERMODRST_OSC1TIMER0_LSB	8
+#define RSTMGR_PERMODRST_UART0_LSB	16
 #define RSTMGR_PERMODRST_SPIM0_LSB	18
 #define RSTMGR_PERMODRST_SPIM1_LSB	19
+#define RSTMGR_PERMODRST_SDR_LSB	29
 
 #endif /* _RESET_MANAGER_H_ */