diff mbox

[[ARM/AArch64,testsuite] 18/36] Add vsli_n and vsri_n tests.

Message ID 1421162314-25779-19-git-send-email-christophe.lyon@linaro.org
State New
Headers show

Commit Message

Christophe Lyon Jan. 13, 2015, 3:18 p.m. UTC 
* gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vsli_n.c: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vsri_n.c: New file.

Comments

Tejas Belagod Jan. 16, 2015, 6:06 p.m. UTC | #1 
> +
> +void vsri_extra(void)
> +{
> +    /* Test cases with maximum shift amount (this amount is different
> +     * from vsli.  */
> +

Nit. Comment Formatting. Similarly, few other places.

Otherwise, LGTM.

Tejas.
Marcus Shawcroft Jan. 19, 2015, 2:11 p.m. UTC | #2 
On 16 January 2015 at 18:06, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> +
>> +void vsri_extra(void)
>> +{
>> +    /* Test cases with maximum shift amount (this amount is different
>> +     * from vsli.  */
>> +
>
>
> Nit. Comment Formatting. Similarly, few other places.
>
> Otherwise, LGTM.
>
> Tejas.
>

w.r.t the unbalanced parenthesis then fair point.  This suite of tests
has numerous gnu style inconsistencies.  Given that Christophe is
importing a pre-existing body of code and that this is in testsuite it
seemed unreasonable to insist on a reformat.  Christophe, fix up the
unbalanced parenthesis and this is OK. /Marcus
diff mbox

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc
new file mode 100644
index 0000000..32c0d86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc
@@ -0,0 +1,82 @@ 
+#define FNNAME1(NAME) exec_ ## NAME ##_n
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+  /* vector_res = vsxi_n(vector, vector2, val),
+     then store the result.  */
+#define TEST_VSXI_N1(INSN, Q, T1, T2, W, N, V)				\
+  VECT_VAR(vector_res, T1, W, N) =					\
+    INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N),			\
+			VECT_VAR(vector2, T1, W, N),			\
+			V);						\
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VSXI_N(INSN, Q, T1, T2, W, N, V)	\
+  TEST_VSXI_N1(INSN, Q, T1, T2, W, N, V)
+
+  DECL_VARIABLE_ALL_VARIANTS(vector);
+  DECL_VARIABLE_ALL_VARIANTS(vector2);
+  DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+  clean_results ();
+
+  /* Initialize input "vector" from "buffer".  */
+  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+  /* Fill input vector2 with arbitrary values.  */
+  VDUP(vector2, , int, s, 8, 8, 2);
+  VDUP(vector2, , int, s, 16, 4, -4);
+  VDUP(vector2, , int, s, 32, 2, 3);
+  VDUP(vector2, , int, s, 64, 1, 100);
+  VDUP(vector2, , uint, u, 8, 8, 20);
+  VDUP(vector2, , uint, u, 16, 4, 30);
+  VDUP(vector2, , uint, u, 32, 2, 40);
+  VDUP(vector2, , uint, u, 64, 1, 2);
+  VDUP(vector2, , poly, p, 8, 8, 20);
+  VDUP(vector2, , poly, p, 16, 4, 30);
+  VDUP(vector2, q, int, s, 8, 16, -10);
+  VDUP(vector2, q, int, s, 16, 8, -20);
+  VDUP(vector2, q, int, s, 32, 4, -30);
+  VDUP(vector2, q, int, s, 64, 2, 24);
+  VDUP(vector2, q, uint, u, 8, 16, 12);
+  VDUP(vector2, q, uint, u, 16, 8, 3);
+  VDUP(vector2, q, uint, u, 32, 4, 55);
+  VDUP(vector2, q, uint, u, 64, 2, 3);
+  VDUP(vector2, q, poly, p, 8, 16, 12);
+  VDUP(vector2, q, poly, p, 16, 8, 3);
+
+  /* Choose shift amount arbitrarily.  */
+  TEST_VSXI_N(INSN_NAME, , int, s, 8, 8, 4);
+  TEST_VSXI_N(INSN_NAME, , int, s, 16, 4, 3);
+  TEST_VSXI_N(INSN_NAME, , int, s, 32, 2, 1);
+  TEST_VSXI_N(INSN_NAME, , int, s, 64, 1, 32);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 8, 8, 2);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 16, 4, 10);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 32, 2, 30);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 64, 1, 3);
+  TEST_VSXI_N(INSN_NAME, , poly, p, 8, 8, 2);
+  TEST_VSXI_N(INSN_NAME, , poly, p, 16, 4, 10);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 8, 16, 5);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 16, 8, 3);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 32, 4, 20);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 64, 2, 16);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 8, 16, 3);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 16, 8, 12);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 32, 4, 23);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 64, 2, 53);
+  TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 3);
+  TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 12);
+
+  CHECK_RESULTS (TEST_MSG, "");
+
+#ifdef EXTRA_TESTS
+  EXTRA_TESTS();
+#endif
+}
+
+int main (void)
+{
+  FNNAME (INSN_NAME) ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
new file mode 100644
index 0000000..342aec5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
@@ -0,0 +1,162 @@ 
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vsli
+#define TEST_MSG "VSLI_N"
+
+/* Extra tests for functions requiring corner cases tests.  */
+void vsli_extra(void);
+#define EXTRA_TESTS vsli_extra
+
+/* Expected results.  */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x20, 0x21, 0x22, 0x23,
+				       0x24, 0x25, 0x26, 0x27 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe0, 0xffe1, 0xffe2, 0xffe3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x6, 0x7 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x64fffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x50, 0x51, 0x52, 0x53,
+					0x50, 0x51, 0x52, 0x53 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x7bf0, 0x7bf1, 0x7bf2, 0x7bf3 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x3ffffff0, 0x3ffffff1 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x10 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x50, 0x51, 0x52, 0x53,
+					0x50, 0x51, 0x52, 0x53 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x7bf0, 0x7bf1, 0x7bf2, 0x7bf3 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xd0, 0xd1, 0xd2, 0xd3,
+					0xd4, 0xd5, 0xd6, 0xd7,
+					0xd8, 0xd9, 0xda, 0xdb,
+					0xdc, 0xdd, 0xde, 0xdf };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xff60, 0xff61, 0xff62, 0xff63,
+					0xff64, 0xff65, 0xff66, 0xff67 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfe2ffff0, 0xfe2ffff1,
+					0xfe2ffff2, 0xfe2ffff3 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x18fff0, 0x18fff1 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x60, 0x61, 0x62, 0x63,
+					 0x64, 0x65, 0x66, 0x67,
+					 0x60, 0x61, 0x62, 0x63,
+					 0x64, 0x65, 0x66, 0x67 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3ff0, 0x3ff1, 0x3ff2, 0x3ff3,
+					 0x3ff4, 0x3ff5, 0x3ff6, 0x3ff7 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x1bfffff0, 0x1bfffff1,
+					 0x1bfffff2, 0x1bfffff3 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x7ffffffffffff0, 0x7ffffffffffff1 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x60, 0x61, 0x62, 0x63,
+					 0x64, 0x65, 0x66, 0x67,
+					 0x60, 0x61, 0x62, 0x63,
+					 0x64, 0x65, 0x66, 0x67 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3ff0, 0x3ff1, 0x3ff2, 0x3ff3,
+					 0x3ff4, 0x3ff5, 0x3ff6, 0x3ff7 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+					   0x33333333, 0x33333333 };
+
+/* Expected results with max shift amount.  */
+VECT_VAR_DECL(expected_max_shift,int,8,8) [] = { 0x70, 0x71, 0x72, 0x73,
+						 0x74, 0x75, 0x76, 0x77 };
+VECT_VAR_DECL(expected_max_shift,int,16,4) [] = { 0x7ff0, 0x7ff1,
+						  0x7ff2, 0x7ff3 };
+VECT_VAR_DECL(expected_max_shift,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_max_shift,int,64,1) [] = { 0x7ffffffffffffff0 };
+VECT_VAR_DECL(expected_max_shift,uint,8,8) [] = { 0x70, 0x71, 0x72, 0x73,
+						  0x74, 0x75, 0x76, 0x77 };
+VECT_VAR_DECL(expected_max_shift,uint,16,4) [] = { 0x7ff0, 0x7ff1,
+						   0x7ff2, 0x7ff3 };
+VECT_VAR_DECL(expected_max_shift,uint,32,2) [] = { 0x7ffffff0, 0x7ffffff1 };
+VECT_VAR_DECL(expected_max_shift,uint,64,1) [] = { 0x7ffffffffffffff0 };
+VECT_VAR_DECL(expected_max_shift,poly,8,8) [] = { 0x70, 0x71, 0x72, 0x73,
+						  0x74, 0x75, 0x76, 0x77 };
+VECT_VAR_DECL(expected_max_shift,poly,16,4) [] = { 0x7ff0, 0x7ff1,
+						   0x7ff2, 0x7ff3 };
+VECT_VAR_DECL(expected_max_shift,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_max_shift,int,8,16) [] = { 0x70, 0x71, 0x72, 0x73,
+						  0x74, 0x75, 0x76, 0x77,
+						  0x78, 0x79, 0x7a, 0x7b,
+						  0x7c, 0x7d, 0x7e, 0x7f };
+VECT_VAR_DECL(expected_max_shift,int,16,8) [] = { 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3,
+						  0x7ff4, 0x7ff5, 0x7ff6, 0x7ff7 };
+VECT_VAR_DECL(expected_max_shift,int,32,4) [] = { 0x7ffffff0, 0x7ffffff1,
+						  0x7ffffff2, 0x7ffffff3 };
+VECT_VAR_DECL(expected_max_shift,int,64,2) [] = { 0x7ffffffffffffff0,
+						  0x7ffffffffffffff1 };
+VECT_VAR_DECL(expected_max_shift,uint,8,16) [] = { 0x70, 0x71, 0x72, 0x73,
+						   0x74, 0x75, 0x76, 0x77,
+						   0x78, 0x79, 0x7a, 0x7b,
+						   0x7c, 0x7d, 0x7e, 0x7f };
+VECT_VAR_DECL(expected_max_shift,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+						   0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_max_shift,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+						   0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_max_shift,uint,64,2) [] = { 0xfffffffffffffff0,
+						   0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_max_shift,poly,8,16) [] = { 0x70, 0x71, 0x72, 0x73,
+						   0x74, 0x75, 0x76, 0x77,
+						   0x78, 0x79, 0x7a, 0x7b,
+						   0x7c, 0x7d, 0x7e, 0x7f };
+VECT_VAR_DECL(expected_max_shift,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+						   0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_max_shift,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+						     0x33333333, 0x33333333 };
+
+#include "vsXi_n.inc"
+
+void vsli_extra(void)
+{
+    /* Test cases with maximum shift amount (this amount is different
+     * from vsri.  */
+
+  DECL_VARIABLE_ALL_VARIANTS(vector);
+  DECL_VARIABLE_ALL_VARIANTS(vector2);
+  DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+  clean_results ();
+
+  /* Initialize input "vector" from "buffer".  */
+  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+  /* Fill input vector2 with arbitrary values.  */
+  VDUP(vector2, , int, s, 8, 8, 2);
+  VDUP(vector2, , int, s, 16, 4, -4);
+  VDUP(vector2, , int, s, 32, 2, 3);
+  VDUP(vector2, , int, s, 64, 1, 100);
+  VDUP(vector2, , uint, u, 8, 8, 20);
+  VDUP(vector2, , uint, u, 16, 4, 30);
+  VDUP(vector2, , uint, u, 32, 2, 40);
+  VDUP(vector2, , uint, u, 64, 1, 2);
+  VDUP(vector2, , poly, p, 8, 8, 20);
+  VDUP(vector2, , poly, p, 16, 4, 30);
+  VDUP(vector2, q, int, s, 8, 16, -10);
+  VDUP(vector2, q, int, s, 16, 8, -20);
+  VDUP(vector2, q, int, s, 32, 4, -30);
+  VDUP(vector2, q, int, s, 64, 2, 24);
+  VDUP(vector2, q, uint, u, 8, 16, 12);
+  VDUP(vector2, q, uint, u, 16, 8, 3);
+  VDUP(vector2, q, uint, u, 32, 4, 55);
+  VDUP(vector2, q, uint, u, 64, 2, 3);
+  VDUP(vector2, q, poly, p, 8, 16, 12);
+  VDUP(vector2, q, poly, p, 16, 8, 3);
+
+  /* Use maximum allowed shift amount.  */
+  TEST_VSXI_N(INSN_NAME, , int, s, 8, 8, 7);
+  TEST_VSXI_N(INSN_NAME, , int, s, 16, 4, 15);
+  TEST_VSXI_N(INSN_NAME, , int, s, 32, 2, 31);
+  TEST_VSXI_N(INSN_NAME, , int, s, 64, 1, 63);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 8, 8, 7);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 16, 4, 15);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 32, 2, 31);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 64, 1, 63);
+  TEST_VSXI_N(INSN_NAME, , poly, p, 8, 8, 7);
+  TEST_VSXI_N(INSN_NAME, , poly, p, 16, 4, 15);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 8, 16, 7);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 16, 8, 15);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 32, 4, 31);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 64, 2, 63);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 8, 16, 7);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 16, 8, 15);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 32, 4, 31);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 64, 2, 63);
+  TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 7);
+  TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 15);
+
+  CHECK_RESULTS_NAMED (TEST_MSG, expected_max_shift, "(max shift amount)");
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c
new file mode 100644
index 0000000..fd85331
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c
@@ -0,0 +1,164 @@ 
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vsri
+#define TEST_MSG "VSRI_N"
+
+/* Extra tests for functions requiring corner cases tests.  */
+void vsri_extra(void);
+#define EXTRA_TESTS vsri_extra
+
+/* Expected results.  */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+				       0xf0, 0xf0, 0xf0, 0xf0 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x80000001, 0x80000001 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffff00000000 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xc5, 0xc5, 0xc5, 0xc5,
+					0xc5, 0xc5, 0xc5, 0xc5 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffc0, 0xffc0, 0xffc0, 0xffc0 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0xe000000000000000 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0xc5, 0xc5, 0xc5, 0xc5,
+					0xc5, 0xc5, 0xc5, 0xc5 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0xffc0, 0xffc0, 0xffc0, 0xffc0 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf7, 0xf7, 0xf7, 0xf7,
+					0xf7, 0xf7, 0xf7, 0xf7,
+					0xff, 0xff, 0xff, 0xff,
+					0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffd, 0xfffd, 0xfffd,
+					0xfffd, 0xfffd, 0xfffd, 0xfffd };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff,
+					0xffffffff, 0xffffffff };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffff000000000000,
+					0xffff000000000000 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xe1, 0xe1, 0xe1, 0xe1,
+					 0xe1, 0xe1, 0xe1, 0xe1,
+					 0xe1, 0xe1, 0xe1, 0xe1,
+					 0xe1, 0xe1, 0xe1, 0xe1 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0,
+					 0xfff0, 0xfff0, 0xfff0, 0xfff0 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffe00, 0xfffffe00,
+					 0xfffffe00, 0xfffffe00 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffff800,
+					 0xfffffffffffff800 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0xe1, 0xe1, 0xe1, 0xe1,
+					 0xe1, 0xe1, 0xe1, 0xe1,
+					 0xe1, 0xe1, 0xe1, 0xe1,
+					 0xe1, 0xe1, 0xe1, 0xe1 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0,
+					 0xfff0, 0xfff0, 0xfff0, 0xfff0 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+					   0x33333333, 0x33333333 };
+
+/* Expected results with max shift amount.  */
+VECT_VAR_DECL(expected_max_shift,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+						 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_max_shift,int,16,4) [] = { 0xfff0, 0xfff1,
+						  0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_max_shift,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_max_shift,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_max_shift,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+						  0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_max_shift,uint,16,4) [] = { 0xfff0, 0xfff1,
+						   0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_max_shift,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_max_shift,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_max_shift,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+						  0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_max_shift,poly,16,4) [] = { 0xfff0, 0xfff1,
+						   0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_max_shift,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_max_shift,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+						  0xf4, 0xf5, 0xf6, 0xf7,
+						  0xf8, 0xf9, 0xfa, 0xfb,
+						  0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_max_shift,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+						  0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_max_shift,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+						  0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_max_shift,int,64,2) [] = { 0xfffffffffffffff0,
+						  0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_max_shift,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+						   0xf4, 0xf5, 0xf6, 0xf7,
+						   0xf8, 0xf9, 0xfa, 0xfb,
+						   0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_max_shift,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+						   0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_max_shift,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+						   0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_max_shift,uint,64,2) [] = { 0xfffffffffffffff0,
+						   0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_max_shift,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+						   0xf4, 0xf5, 0xf6, 0xf7,
+						   0xf8, 0xf9, 0xfa, 0xfb,
+						   0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_max_shift,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+						   0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_max_shift,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+						     0x33333333, 0x33333333 };
+
+#include "vsXi_n.inc"
+
+void vsri_extra(void)
+{
+    /* Test cases with maximum shift amount (this amount is different
+     * from vsli.  */
+
+  DECL_VARIABLE_ALL_VARIANTS(vector);
+  DECL_VARIABLE_ALL_VARIANTS(vector2);
+  DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+  clean_results ();
+
+  /* Initialize input "vector" from "buffer".  */
+  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+  /* Fill input vector2 with arbitrary values.  */
+  VDUP(vector2, , int, s, 8, 8, 2);
+  VDUP(vector2, , int, s, 16, 4, -4);
+  VDUP(vector2, , int, s, 32, 2, 3);
+  VDUP(vector2, , int, s, 64, 1, 100);
+  VDUP(vector2, , uint, u, 8, 8, 20);
+  VDUP(vector2, , uint, u, 16, 4, 30);
+  VDUP(vector2, , uint, u, 32, 2, 40);
+  VDUP(vector2, , uint, u, 64, 1, 2);
+  VDUP(vector2, , poly, p, 8, 8, 20);
+  VDUP(vector2, , poly, p, 16, 4, 30);
+  VDUP(vector2, q, int, s, 8, 16, -10);
+  VDUP(vector2, q, int, s, 16, 8, -20);
+  VDUP(vector2, q, int, s, 32, 4, -30);
+  VDUP(vector2, q, int, s, 64, 2, 24);
+  VDUP(vector2, q, uint, u, 8, 16, 12);
+  VDUP(vector2, q, uint, u, 16, 8, 3);
+  VDUP(vector2, q, uint, u, 32, 4, 55);
+  VDUP(vector2, q, uint, u, 64, 2, 3);
+  VDUP(vector2, q, poly, p, 8, 16, 12);
+  VDUP(vector2, q, poly, p, 16, 8, 3);
+
+  /* Use maximum allowed shift amount.  */
+  TEST_VSXI_N(INSN_NAME, , int, s, 8, 8, 8);
+  TEST_VSXI_N(INSN_NAME, , int, s, 16, 4, 16);
+  TEST_VSXI_N(INSN_NAME, , int, s, 32, 2, 32);
+  TEST_VSXI_N(INSN_NAME, , int, s, 64, 1, 64);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 8, 8, 8);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 16, 4, 16);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 32, 2, 32);
+  TEST_VSXI_N(INSN_NAME, , uint, u, 64, 1, 64);
+  TEST_VSXI_N(INSN_NAME, , poly, p, 8, 8, 8);
+  TEST_VSXI_N(INSN_NAME, , poly, p, 16, 4, 16);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 8, 16, 8);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 16, 8, 16);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 32, 4, 32);
+  TEST_VSXI_N(INSN_NAME, q, int, s, 64, 2, 64);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 8, 16, 8);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 16, 8, 16);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 32, 4, 32);
+  TEST_VSXI_N(INSN_NAME, q, uint, u, 64, 2, 64);
+  TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 8);
+  TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 16);
+
+  CHECK_RESULTS_NAMED (TEST_MSG, expected_max_shift, "(max shift amount)");
+}