diff mbox

[[ARM/AArch64,testsuite] 10/36] Add vmlal and vmlsl tests.

Message ID 1421162314-25779-11-git-send-email-christophe.lyon@linaro.org
State New
Headers show

Commit Message

Christophe Lyon Jan. 13, 2015, 3:18 p.m. UTC 
* gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vmlal.c: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vmlsl.c: New file.

Comments

Tejas Belagod Jan. 16, 2015, 4:13 p.m. UTC | #1 
On 13/01/15 15:18, Christophe Lyon wrote:
> 	* gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc: New file.
> 	* gcc.target/aarch64/advsimd-intrinsics/vmlal.c: New file.
> 	* gcc.target/aarch64/advsimd-intrinsics/vmlsl.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc
> new file mode 100644
> index 0000000..1e6bab3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc
> @@ -0,0 +1,89 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> +  /* vector_res = OP(vector, vector3, vector4),
> +     then store the result.  */
> +#define TEST_VMLXL1(INSN, T1, T2, W, W2, N)				\
> +  VECT_VAR(vector_res, T1, W, N) =                                      \
> +    INSN##_##T2##W2(VECT_VAR(vector, T1, W, N),                         \
> +                    VECT_VAR(vector3, T1, W2, N),                       \
> +                    VECT_VAR(vector4, T1, W2, N));                      \
> +  vst1q_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
> +
> +#define TEST_VMLXL(INSN, T1, T2, W, W2, N)	\
> +  TEST_VMLXL1(INSN, T1, T2, W, W2, N)
> +
> +  DECL_VARIABLE(vector, int, 16, 8);
> +  DECL_VARIABLE(vector3, int, 8, 8);
> +  DECL_VARIABLE(vector4, int, 8, 8);
> +  DECL_VARIABLE(vector_res, int, 16, 8);
> +
> +  DECL_VARIABLE(vector, int, 32, 4);
> +  DECL_VARIABLE(vector3, int, 16, 4);
> +  DECL_VARIABLE(vector4, int, 16, 4);
> +  DECL_VARIABLE(vector_res, int, 32, 4);
> +
> +  DECL_VARIABLE(vector, int, 64, 2);
> +  DECL_VARIABLE(vector3, int, 32, 2);
> +  DECL_VARIABLE(vector4, int, 32, 2);
> +  DECL_VARIABLE(vector_res, int, 64, 2);
> +
> +  DECL_VARIABLE(vector, uint, 16, 8);
> +  DECL_VARIABLE(vector3, uint, 8, 8);
> +  DECL_VARIABLE(vector4, uint, 8, 8);
> +  DECL_VARIABLE(vector_res, uint, 16, 8);
> +
> +  DECL_VARIABLE(vector, uint, 32, 4);
> +  DECL_VARIABLE(vector3, uint, 16, 4);
> +  DECL_VARIABLE(vector4, uint, 16, 4);
> +  DECL_VARIABLE(vector_res, uint, 32, 4);
> +
> +  DECL_VARIABLE(vector, uint, 64, 2);
> +  DECL_VARIABLE(vector3, uint, 32, 2);
> +  DECL_VARIABLE(vector4, uint, 32, 2);
> +  DECL_VARIABLE(vector_res, uint, 64, 2);
> +
> +  clean_results ();
> +
> +  VLOAD(vector, buffer, q, int, s, 16, 8);
> +  VLOAD(vector, buffer, q, int, s, 32, 4);
> +  VLOAD(vector, buffer, q, int, s, 64, 2);
> +  VLOAD(vector, buffer, q, uint, u, 16, 8);
> +  VLOAD(vector, buffer, q, uint, u, 32, 4);
> +  VLOAD(vector, buffer, q, uint, u, 64, 2);
> +
> +  VDUP(vector3, , int, s, 8, 8, 0x55);
> +  VDUP(vector4, , int, s, 8, 8, 0xBB);
> +  VDUP(vector3, , int, s, 16, 4, 0x55);
> +  VDUP(vector4, , int, s, 16, 4, 0xBB);
> +  VDUP(vector3, , int, s, 32, 2, 0x55);
> +  VDUP(vector4, , int, s, 32, 2, 0xBB);
> +  VDUP(vector3, , uint, u, 8, 8, 0x55);
> +  VDUP(vector4, , uint, u, 8, 8, 0xBB);
> +  VDUP(vector3, , uint, u, 16, 4, 0x55);
> +  VDUP(vector4, , uint, u, 16, 4, 0xBB);
> +  VDUP(vector3, , uint, u, 32, 2, 0x55);
> +  VDUP(vector4, , uint, u, 32, 2, 0xBB);
> +
> +  TEST_VMLXL(INSN_NAME, int, s, 16, 8, 8);
> +  TEST_VMLXL(INSN_NAME, int, s, 32, 16, 4);
> +  TEST_VMLXL(INSN_NAME, int, s, 64, 32, 2);
> +  TEST_VMLXL(INSN_NAME, uint, u, 16, 8, 8);
> +  TEST_VMLXL(INSN_NAME, uint, u, 32, 16, 4);
> +  TEST_VMLXL(INSN_NAME, uint, u, 64, 32, 2);
> +
> +  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
> +  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> +  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
> +  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
> +  CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
> +  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
> +}
> +
> +int main (void)
> +{
> +  FNNAME (INSN_NAME) ();
> +  return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c
> new file mode 100644
> index 0000000..c147f31
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c
> @@ -0,0 +1,18 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vmlal
> +#define TEST_MSG "VMLAL"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xe907, 0xe908, 0xe909, 0xe90a,
> +					0xe90b, 0xe90c, 0xe90d, 0xe90e };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3e07, 0x3e08 };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a,
> +					 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3e07, 0x3e08 };
> +
> +#include "vmlXl.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c
> new file mode 100644
> index 0000000..6c984ae
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c
> @@ -0,0 +1,22 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vmlsl
> +#define TEST_MSG "VMLSL"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0x16d9, 0x16da, 0x16db, 0x16dc,
> +					0x16dd, 0x16de, 0x16df, 0x16e0 };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffc1d9, 0xffffc1da,
> +					0xffffc1db, 0xffffc1dc };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffc1d9,
> +					0xffffffffffffc1da };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc,
> +					 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc1d9, 0xffffc1da,
> +					 0xffffc1db, 0xffffc1dc };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffc1d9,
> +					 0xffffffffffffc1da };
> +
> +#include "vmlXl.inc"
>

LGTM.

Tejas.
Marcus Shawcroft Jan. 19, 2015, 1:43 p.m. UTC | #2 
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>         * gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc: New file.
>         * gcc.target/aarch64/advsimd-intrinsics/vmlal.c: New file.
>         * gcc.target/aarch64/advsimd-intrinsics/vmlsl.c: New file.

OK /Marcus
diff mbox

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc
new file mode 100644
index 0000000..1e6bab3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc
@@ -0,0 +1,89 @@ 
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+  /* vector_res = OP(vector, vector3, vector4),
+     then store the result.  */
+#define TEST_VMLXL1(INSN, T1, T2, W, W2, N)				\
+  VECT_VAR(vector_res, T1, W, N) =                                      \
+    INSN##_##T2##W2(VECT_VAR(vector, T1, W, N),                         \
+                    VECT_VAR(vector3, T1, W2, N),                       \
+                    VECT_VAR(vector4, T1, W2, N));                      \
+  vst1q_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLXL(INSN, T1, T2, W, W2, N)	\
+  TEST_VMLXL1(INSN, T1, T2, W, W2, N)
+
+  DECL_VARIABLE(vector, int, 16, 8);
+  DECL_VARIABLE(vector3, int, 8, 8);
+  DECL_VARIABLE(vector4, int, 8, 8);
+  DECL_VARIABLE(vector_res, int, 16, 8);
+
+  DECL_VARIABLE(vector, int, 32, 4);
+  DECL_VARIABLE(vector3, int, 16, 4);
+  DECL_VARIABLE(vector4, int, 16, 4);
+  DECL_VARIABLE(vector_res, int, 32, 4);
+
+  DECL_VARIABLE(vector, int, 64, 2);
+  DECL_VARIABLE(vector3, int, 32, 2);
+  DECL_VARIABLE(vector4, int, 32, 2);
+  DECL_VARIABLE(vector_res, int, 64, 2);
+
+  DECL_VARIABLE(vector, uint, 16, 8);
+  DECL_VARIABLE(vector3, uint, 8, 8);
+  DECL_VARIABLE(vector4, uint, 8, 8);
+  DECL_VARIABLE(vector_res, uint, 16, 8);
+
+  DECL_VARIABLE(vector, uint, 32, 4);
+  DECL_VARIABLE(vector3, uint, 16, 4);
+  DECL_VARIABLE(vector4, uint, 16, 4);
+  DECL_VARIABLE(vector_res, uint, 32, 4);
+
+  DECL_VARIABLE(vector, uint, 64, 2);
+  DECL_VARIABLE(vector3, uint, 32, 2);
+  DECL_VARIABLE(vector4, uint, 32, 2);
+  DECL_VARIABLE(vector_res, uint, 64, 2);
+
+  clean_results ();
+
+  VLOAD(vector, buffer, q, int, s, 16, 8);
+  VLOAD(vector, buffer, q, int, s, 32, 4);
+  VLOAD(vector, buffer, q, int, s, 64, 2);
+  VLOAD(vector, buffer, q, uint, u, 16, 8);
+  VLOAD(vector, buffer, q, uint, u, 32, 4);
+  VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+  VDUP(vector3, , int, s, 8, 8, 0x55);
+  VDUP(vector4, , int, s, 8, 8, 0xBB);
+  VDUP(vector3, , int, s, 16, 4, 0x55);
+  VDUP(vector4, , int, s, 16, 4, 0xBB);
+  VDUP(vector3, , int, s, 32, 2, 0x55);
+  VDUP(vector4, , int, s, 32, 2, 0xBB);
+  VDUP(vector3, , uint, u, 8, 8, 0x55);
+  VDUP(vector4, , uint, u, 8, 8, 0xBB);
+  VDUP(vector3, , uint, u, 16, 4, 0x55);
+  VDUP(vector4, , uint, u, 16, 4, 0xBB);
+  VDUP(vector3, , uint, u, 32, 2, 0x55);
+  VDUP(vector4, , uint, u, 32, 2, 0xBB);
+
+  TEST_VMLXL(INSN_NAME, int, s, 16, 8, 8);
+  TEST_VMLXL(INSN_NAME, int, s, 32, 16, 4);
+  TEST_VMLXL(INSN_NAME, int, s, 64, 32, 2);
+  TEST_VMLXL(INSN_NAME, uint, u, 16, 8, 8);
+  TEST_VMLXL(INSN_NAME, uint, u, 32, 16, 4);
+  TEST_VMLXL(INSN_NAME, uint, u, 64, 32, 2);
+
+  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+  CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+  FNNAME (INSN_NAME) ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c
new file mode 100644
index 0000000..c147f31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c
@@ -0,0 +1,18 @@ 
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlal
+#define TEST_MSG "VMLAL"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xe907, 0xe908, 0xe909, 0xe90a,
+					0xe90b, 0xe90c, 0xe90d, 0xe90e };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3e07, 0x3e08 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a,
+					 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3e07, 0x3e08 };
+
+#include "vmlXl.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c
new file mode 100644
index 0000000..6c984ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c
@@ -0,0 +1,22 @@ 
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlsl
+#define TEST_MSG "VMLSL"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x16d9, 0x16da, 0x16db, 0x16dc,
+					0x16dd, 0x16de, 0x16df, 0x16e0 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffc1d9, 0xffffc1da,
+					0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffc1d9,
+					0xffffffffffffc1da };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc,
+					 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc1d9, 0xffffc1da,
+					 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffc1d9,
+					 0xffffffffffffc1da };
+
+#include "vmlXl.inc"