| Message ID | 1421093739-41520-4-git-send-email-philipp.tomsich@theobroma-systems.com |
|---|---|
| State | New |
| Headers | show |
On 12/01/15 20:15, Philipp Tomsich wrote: > --- > gcc/config/aarch64/aarch64.md | 2 +- > gcc/config/arm/types.md | 2 ++ > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 1f6b1b6..98f4f30 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -391,7 +391,7 @@ > > return pftype[INTVAL(operands[1])][locality]; > } > - [(set_attr "type" "load1")] > + [(set_attr "type" "prefetch")] > ) > > (define_insn "trap" > diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md > index d368446..088c21a 100644 > --- a/gcc/config/arm/types.md > +++ b/gcc/config/arm/types.md > @@ -118,6 +118,7 @@ > ; mvn_shift_reg inverting move instruction, shifted operand by a register. > ; no_insn an insn which does not represent an instruction in the > ; final output, thus having no impact on scheduling. > +; prefetch a prefetch instruction > ; rbit reverse bits. > ; rev reverse bytes. > ; sdiv signed division. > @@ -556,6 +557,7 @@ > call,\ > clz,\ > no_insn,\ > + prefetch,\ > csel,\ > crc,\ > extend,\ > Can you follow up with a patch that adjusts the "prefetch" insn attribute in the ARM backend and uses this consistently in all the pipeline descriptions (i.e. treat this equivalent to load1 and make sure the compiler builds for AArch32 afterwards) ? It would be complete to do the same for all the pipeline descriptions in the AArch64 backend too. Ramana
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 1f6b1b6..98f4f30 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -391,7 +391,7 @@ return pftype[INTVAL(operands[1])][locality]; } - [(set_attr "type" "load1")] + [(set_attr "type" "prefetch")] ) (define_insn "trap" diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index d368446..088c21a 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -118,6 +118,7 @@ ; mvn_shift_reg inverting move instruction, shifted operand by a register. ; no_insn an insn which does not represent an instruction in the ; final output, thus having no impact on scheduling. +; prefetch a prefetch instruction ; rbit reverse bits. ; rev reverse bytes. ; sdiv signed division. @@ -556,6 +557,7 @@ call,\ clz,\ no_insn,\ + prefetch,\ csel,\ crc,\ extend,\