| Message ID | 1421079427-8418-1-git-send-email-vladimir.barinov@cogentembedded.com |
|---|---|
| State | Accepted |
| Delegated to: | Nobuhiro Iwamatsu |
| Headers | show |
On Mon, Jan 12, 2015 at 07:17:07PM +0300, Vladimir Barinov wrote: > SILK is an entry level development board based on R-Car E2 SoC (R8A7794) > > This commit supports the following peripherals: > - SCIF, I2C, Ethernet, QSPI, MMC, USB Host > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by: Tom Rini <trini@ti.com>
Hi, Vladimir. Applied, thanks. Best regards, Nobuhiro 2015-01-13 1:17 GMT+09:00 Vladimir Barinov <vladimir.barinov@cogentembedded.com>: > SILK is an entry level development board based on R-Car E2 SoC (R8A7794) > > This commit supports the following peripherals: > - SCIF, I2C, Ethernet, QSPI, MMC, USB Host > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > --- > arch/arm/cpu/armv7/rmobile/Kconfig | 6 +- > board/renesas/silk/Kconfig | 12 + > board/renesas/silk/MAINTAINERS | 6 + > board/renesas/silk/Makefile | 10 + > board/renesas/silk/qos.c | 951 +++++++++++++++++++++++++++++++++++++ > board/renesas/silk/silk.c | 175 +++++++ > configs/silk_defconfig | 3 + > include/configs/silk.h | 117 +++++ > 8 files changed, 1279 insertions(+), 1 deletion(-) > create mode 100644 board/renesas/silk/Kconfig > create mode 100644 board/renesas/silk/MAINTAINERS > create mode 100644 board/renesas/silk/Makefile > create mode 100644 board/renesas/silk/qos.c > create mode 100644 board/renesas/silk/silk.c > create mode 100644 configs/silk_defconfig > create mode 100644 include/configs/silk.h > > diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig > index 6d94199..3586650 100644 > --- a/arch/arm/cpu/armv7/rmobile/Kconfig > +++ b/arch/arm/cpu/armv7/rmobile/Kconfig > @@ -21,6 +21,9 @@ config TARGET_KZM9G > config TARGET_ALT > bool "Alt board" > > +config TARGET_SILK > + bool "Silk board" > + > endchoice > > config SYS_SOC > @@ -28,7 +31,7 @@ config SYS_SOC > > config RMOBILE_EXTRAM_BOOT > bool "Enable boot from RAM" > - depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER > + depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK > default n > > source "board/atmark-techno/armadillo-800eva/Kconfig" > @@ -37,5 +40,6 @@ source "board/renesas/koelsch/Kconfig" > source "board/renesas/lager/Kconfig" > source "board/kmc/kzm9g/Kconfig" > source "board/renesas/alt/Kconfig" > +source "board/renesas/silk/Kconfig" > > endif > diff --git a/board/renesas/silk/Kconfig b/board/renesas/silk/Kconfig > new file mode 100644 > index 0000000..07aee0e > --- /dev/null > +++ b/board/renesas/silk/Kconfig > @@ -0,0 +1,12 @@ > +if TARGET_SILK > + > +config SYS_BOARD > + default "silk" > + > +config SYS_VENDOR > + default "renesas" > + > +config SYS_CONFIG_NAME > + default "silk" > + > +endif > diff --git a/board/renesas/silk/MAINTAINERS b/board/renesas/silk/MAINTAINERS > new file mode 100644 > index 0000000..b566ccf > --- /dev/null > +++ b/board/renesas/silk/MAINTAINERS > @@ -0,0 +1,6 @@ > +SILK BOARD > +M: Cogent Embedded, Inc. <source@cogentembedded.com> > +S: Maintained > +F: board/renesas/silk/ > +F: include/configs/silk.h > +F: configs/silk_defconfig > diff --git a/board/renesas/silk/Makefile b/board/renesas/silk/Makefile > new file mode 100644 > index 0000000..e6eea61 > --- /dev/null > +++ b/board/renesas/silk/Makefile > @@ -0,0 +1,10 @@ > +# > +# board/renesas/silk/Makefile > +# > +# Copyright (C) 2015 Renesas Electronics Corporation > +# Copyright (C) 2015 Cogent Embedded, Inc. > +# > +# SPDX-License-Identifier: GPL-2.0 > +# > + > +obj-y := silk.o qos.o ../rcar-gen2-common/common.o > diff --git a/board/renesas/silk/qos.c b/board/renesas/silk/qos.c > new file mode 100644 > index 0000000..4f6e46c > --- /dev/null > +++ b/board/renesas/silk/qos.c > @@ -0,0 +1,951 @@ > +/* > + * board/renesas/silk/qos.c > + * > + * Copyright (C) 2015 Renesas Electronics Corporation > + * Copyright (C) 2015 Cogent Embedded, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0 > + * > + */ > + > +#include <common.h> > +#include <asm/processor.h> > +#include <asm/mach-types.h> > +#include <asm/io.h> > +#include <asm/arch/rmobile.h> > + > +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) > +/* QoS version 0.11 */ > + > +enum { > + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, > + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, > + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, > + DBSC3_15, > + DBSC3_NR, > +}; > + > +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { > + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, > + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, > + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, > + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, > + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, > + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, > + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, > + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, > + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, > + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, > + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, > + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, > + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, > + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, > + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, > + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, > +}; > + > +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { > + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, > + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, > + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, > + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, > + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, > + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, > + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, > + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, > + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, > + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, > + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, > + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, > + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, > + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, > + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, > + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, > +}; > + > +void qos_init(void) > +{ > + int i; > + struct rcar_s3c *s3c; > + struct rcar_s3c_qos *s3c_qos; > + struct rcar_dbsc3_qos *qos_addr; > + struct rcar_mxi *mxi; > + struct rcar_mxi_qos *mxi_qos; > + struct rcar_axi_qos *axi_qos; > + > + /* DBSC DBADJ2 */ > + writel(0x20042004, DBSC3_0_DBADJ2); > + > + /* S3C -QoS */ > + s3c = (struct rcar_s3c *)S3C_BASE; > + writel(0x1F0D0B0A, &s3c->s3crorr); > + writel(0x1F0D0B09, &s3c->s3cworr); > + > + /* QoS Control Registers */ > + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; > + writel(0x00890089, &s3c_qos->s3cqos0); > + writel(0x20960010, &s3c_qos->s3cqos1); > + writel(0x20302030, &s3c_qos->s3cqos2); > + writel(0x20AA2200, &s3c_qos->s3cqos3); > + writel(0x00002032, &s3c_qos->s3cqos4); > + writel(0x20960010, &s3c_qos->s3cqos5); > + writel(0x20302030, &s3c_qos->s3cqos6); > + writel(0x20AA2200, &s3c_qos->s3cqos7); > + writel(0x00002032, &s3c_qos->s3cqos8); > + > + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; > + writel(0x00890089, &s3c_qos->s3cqos0); > + writel(0x20960010, &s3c_qos->s3cqos1); > + writel(0x20302030, &s3c_qos->s3cqos2); > + writel(0x20AA2200, &s3c_qos->s3cqos3); > + writel(0x00002032, &s3c_qos->s3cqos4); > + writel(0x20960010, &s3c_qos->s3cqos5); > + writel(0x20302030, &s3c_qos->s3cqos6); > + writel(0x20AA2200, &s3c_qos->s3cqos7); > + writel(0x00002032, &s3c_qos->s3cqos8); > + > + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; > + writel(0x80928092, &s3c_qos->s3cqos0); > + writel(0x20960020, &s3c_qos->s3cqos1); > + writel(0x20302030, &s3c_qos->s3cqos2); > + writel(0x20AA20DC, &s3c_qos->s3cqos3); > + writel(0x00002032, &s3c_qos->s3cqos4); > + writel(0x20960020, &s3c_qos->s3cqos5); > + writel(0x20302030, &s3c_qos->s3cqos6); > + writel(0x20AA20DC, &s3c_qos->s3cqos7); > + writel(0x00002032, &s3c_qos->s3cqos8); > + > + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; > + writel(0x00820082, &s3c_qos->s3cqos0); > + writel(0x20960020, &s3c_qos->s3cqos1); > + writel(0x20302030, &s3c_qos->s3cqos2); > + writel(0x20AA20FA, &s3c_qos->s3cqos3); > + writel(0x00002032, &s3c_qos->s3cqos4); > + writel(0x20960020, &s3c_qos->s3cqos5); > + writel(0x20302030, &s3c_qos->s3cqos6); > + writel(0x20AA20FA, &s3c_qos->s3cqos7); > + writel(0x00002032, &s3c_qos->s3cqos8); > + > + /* DBSC -QoS */ > + /* DBSC0 - Read */ > + for (i = DBSC3_00; i < DBSC3_NR; i++) { > + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; > + writel(0x00000002, &qos_addr->dblgcnt); > + writel(0x0000207D, &qos_addr->dbtmval0); > + writel(0x00002053, &qos_addr->dbtmval1); > + writel(0x0000202A, &qos_addr->dbtmval2); > + writel(0x00001FBD, &qos_addr->dbtmval3); > + writel(0x00000001, &qos_addr->dbrqctr); > + writel(0x00002064, &qos_addr->dbthres0); > + writel(0x0000203E, &qos_addr->dbthres1); > + writel(0x00002019, &qos_addr->dbthres2); > + writel(0x00000001, &qos_addr->dblgqon); > + } > + > + /* DBSC0 - Write */ > + for (i = DBSC3_00; i < DBSC3_NR; i++) { > + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; > + writel(0x00000002, &qos_addr->dblgcnt); > + writel(0x0000207D, &qos_addr->dbtmval0); > + writel(0x00002053, &qos_addr->dbtmval1); > + writel(0x00002043, &qos_addr->dbtmval2); > + writel(0x00002030, &qos_addr->dbtmval3); > + writel(0x00000001, &qos_addr->dbrqctr); > + writel(0x00002064, &qos_addr->dbthres0); > + writel(0x0000203E, &qos_addr->dbthres1); > + writel(0x00002031, &qos_addr->dbthres2); > + writel(0x00000001, &qos_addr->dblgqon); > + } > + > + /* CCI-400 -QoS */ > + writel(0x20000800, CCI_400_MAXOT_1); > + writel(0x20000800, CCI_400_MAXOT_2); > + writel(0x0000000C, CCI_400_QOSCNTL_1); > + writel(0x0000000C, CCI_400_QOSCNTL_2); > + > + /* MXI -QoS */ > + /* Transaction Control (MXI) */ > + mxi = (struct rcar_mxi *)MXI_BASE; > + writel(0x00000013, &mxi->mxrtcr); > + writel(0x00000013, &mxi->mxwtcr); > + writel(0x00780080, &mxi->mxsaar0); > + writel(0x02000800, &mxi->mxsaar1); > + > + /* QoS Control (MXI) */ > + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; > + writel(0x0000000C, &mxi_qos->vspdu0); > + writel(0x0000000E, &mxi_qos->du0); > + > + /* AXI -QoS */ > + /* Transaction Control (MXI) */ > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020A6, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x0000214C, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020A6, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020A6, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002029, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020A6, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x0000214C, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x0000214C, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x000020A6, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + /* QoS Register (RT-AXI) */ > + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + /* QoS Register (MP-AXI) */ > + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002037, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002014, &axi_qos->qosctset0); > + writel(0x00000040, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002014, &axi_qos->qosctset0); > + writel(0x00000040, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00001FF0, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00002001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x00002053, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; > + writel(0x00000000, &axi_qos->qosconf); > + writel(0x0000206E, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + /* QoS Register (SYS-AXI256) */ > + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x000020EB, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x000020EB, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x000020EB, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x000020EB, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + /* QoS Register (CCI-AXI) */ > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x00002245, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002004, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000000, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + /* QoS Register (Media-AXI) */ > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x000020DC, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x000020AA, &axi_qos->qosthres0); > + writel(0x00002032, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; > + writel(0x00000002, &axi_qos->qosconf); > + writel(0x000020DC, &axi_qos->qosctset0); > + writel(0x00002096, &axi_qos->qosctset1); > + writel(0x00002030, &axi_qos->qosctset2); > + writel(0x00002030, &axi_qos->qosctset3); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x000020AA, &axi_qos->qosthres0); > + writel(0x00002032, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002190, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00001FF0, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00002001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; > + writel(0x00000003, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; > + writel(0x00000003, &axi_qos->qosconf); > + writel(0x000020C8, &axi_qos->qosctset0); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; > + writel(0x00000003, &axi_qos->qosconf); > + writel(0x00002063, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; > + writel(0x00000003, &axi_qos->qosconf); > + writel(0x00002063, &axi_qos->qosctset0); > + writel(0x00000001, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002073, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002073, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002073, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002073, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00000001, &axi_qos->qosthres0); > + writel(0x00000001, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > + > + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; > + writel(0x00000001, &axi_qos->qosconf); > + writel(0x00002073, &axi_qos->qosctset0); > + writel(0x00000020, &axi_qos->qosreqctr); > + writel(0x00002064, &axi_qos->qosthres0); > + writel(0x00002004, &axi_qos->qosthres1); > + writel(0x00000001, &axi_qos->qosthres2); > + writel(0x00000001, &axi_qos->qosqon); > +} > +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ > +void qos_init(void) > +{ > +} > +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ > diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c > new file mode 100644 > index 0000000..8818211 > --- /dev/null > +++ b/board/renesas/silk/silk.c > @@ -0,0 +1,175 @@ > +/* > + * board/renesas/silk/silk.c > + * > + * Copyright (C) 2015 Renesas Electronics Corporation > + * Copyright (C) 2015 Cogent Embedded, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0 > + */ > + > +#include <common.h> > +#include <malloc.h> > +#include <asm/processor.h> > +#include <asm/mach-types.h> > +#include <asm/io.h> > +#include <asm/errno.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/gpio.h> > +#include <asm/arch/rmobile.h> > +#include <asm/arch/rcar-mstp.h> > +#include <asm/arch/mmc.h> > +#include <netdev.h> > +#include <miiphy.h> > +#include <i2c.h> > +#include <div64.h> > +#include "qos.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define CLK2MHZ(clk) (clk / 1000 / 1000) > +void s_init(void) > +{ > + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; > + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; > + > + /* Watchdog init */ > + writel(0xA5A5A500, &rwdt->rwtcsra); > + writel(0xA5A5A500, &swdt->swtcsra); > + > + /* QoS */ > + qos_init(); > + > +#ifndef CONFIG_DCACHE_OFF > + /* > + * The caches are disabled when ACTLR.SMP is set to 0 > + * regardless of the value of the SCTLR.C (cache enable bit) > + * on Cortex-A7 MPCore > + */ > + asm volatile( > + "mrc 15, 0, r0, c1, c0, 1\n" /* read ACTLR */ > + "orr r0, r0, #(1 << 6)\n" /* set ACTLR.SMP bit */ > + "mcr p15, 0, r0, c1, c0, 1\n"); /* write ACTLR */ > +#endif > +} > + > +#define TMU0_MSTP125 (1 << 25) > +#define SCIF2_MSTP719 (1 << 19) > +#define ETHER_MSTP813 (1 << 13) > +#define IIC1_MSTP323 (1 << 23) > +#define MMC0_MSTP315 (1 << 15) > + > +int board_early_init_f(void) > +{ > + /* TMU */ > + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); > + > + /* SCIF2 */ > + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); > + > + /* ETHER */ > + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); > + > + /* IIC1 / sh-i2c ch1 */ > + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); > + > +#ifdef CONFIG_SH_MMCIF > + /* MMC */ > + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); > +#endif > + return 0; > +} > + > +int board_init(void) > +{ > + /* adress of boot parameters */ > + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; > + > + /* Init PFC controller */ > + r8a7794_pinmux_init(); > + > + /* Ether Enable */ > + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); > + gpio_request(GPIO_FN_ETH_RX_ER, NULL); > + gpio_request(GPIO_FN_ETH_RXD0, NULL); > + gpio_request(GPIO_FN_ETH_RXD1, NULL); > + gpio_request(GPIO_FN_ETH_LINK, NULL); > + gpio_request(GPIO_FN_ETH_REFCLK, NULL); > + gpio_request(GPIO_FN_ETH_MDIO, NULL); > + gpio_request(GPIO_FN_ETH_TXD1, NULL); > + gpio_request(GPIO_FN_ETH_TX_EN, NULL); > + gpio_request(GPIO_FN_ETH_MAGIC, NULL); > + gpio_request(GPIO_FN_ETH_TXD0, NULL); > + gpio_request(GPIO_FN_ETH_MDC, NULL); > + gpio_request(GPIO_FN_IRQ8, NULL); > + > + /* PHY reset */ > + gpio_request(GPIO_GP_1_24, NULL); > + gpio_direction_output(GPIO_GP_1_24, 0); > + mdelay(20); > + gpio_set_value(GPIO_GP_1_24, 1); > + udelay(1); > + > + return 0; > +} > + > +#define CXR24 0xEE7003C0 /* MAC address high register */ > +#define CXR25 0xEE7003C8 /* MAC address low register */ > +int board_eth_init(bd_t *bis) > +{ > +#ifdef CONFIG_SH_ETHER > + int ret = -ENODEV; > + u32 val; > + unsigned char enetaddr[6]; > + > + ret = sh_eth_initialize(bis); > + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) > + return ret; > + > + /* Set Mac address */ > + val = enetaddr[0] << 24 | enetaddr[1] << 16 | > + enetaddr[2] << 8 | enetaddr[3]; > + writel(val, CXR24); > + > + val = enetaddr[4] << 8 | enetaddr[5]; > + writel(val, CXR25); > + > + return ret; > +#else > + return 0; > +#endif > +} > + > +int board_mmc_init(bd_t *bis) > +{ > + int ret = 0; > + > +#ifdef CONFIG_SH_MMCIF > + /* MMC0 */ > + gpio_request(GPIO_GP_4_31, NULL); > + gpio_set_value(GPIO_GP_4_31, 1); > + > + ret = mmcif_mmc_init(); > +#endif > + return ret; > +} > + > +int dram_init(void) > +{ > + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; > + > + return 0; > +} > + > +const struct rmobile_sysinfo sysinfo = { > + CONFIG_RMOBILE_BOARD_STRING > +}; > + > +void reset_cpu(ulong addr) > +{ > + u8 val; > + > + i2c_set_bus_num(1); /* PowerIC connected to ch1 */ > + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); > + val |= 0x02; > + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); > +} > diff --git a/configs/silk_defconfig b/configs/silk_defconfig > new file mode 100644 > index 0000000..515ee33 > --- /dev/null > +++ b/configs/silk_defconfig > @@ -0,0 +1,3 @@ > +CONFIG_ARM=y > +CONFIG_RMOBILE=y > +CONFIG_TARGET_SILK=y > diff --git a/include/configs/silk.h b/include/configs/silk.h > new file mode 100644 > index 0000000..a4235e9 > --- /dev/null > +++ b/include/configs/silk.h > @@ -0,0 +1,117 @@ > +/* > + * include/configs/silk.h > + * This file is silk board configuration. > + * > + * Copyright (C) 2015 Renesas Electronics Corporation > + * Copyright (C) 2015 Cogent Embedded, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0 > + */ > + > +#ifndef __SILK_H > +#define __SILK_H > + > +#undef DEBUG > +#define CONFIG_R8A7794 > +#define CONFIG_RMOBILE_BOARD_STRING "Silk" > + > +#include "rcar-gen2-common.h" > + > +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) > +#define CONFIG_SYS_TEXT_BASE 0x70000000 > +#else > +#define CONFIG_SYS_TEXT_BASE 0xE6304000 > +#endif > + > +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) > +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC > +#else > +#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC > +#endif > +#define STACK_AREA_SIZE 0xC000 > +#define LOW_LEVEL_MERAM_STACK \ > + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) > + > +/* MEMORY */ > +#define RCAR_GEN2_SDRAM_BASE 0x40000000 > +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) > +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) > + > +/* SCIF */ > +#define CONFIG_SCIF_CONSOLE > +#define CONFIG_CONS_SCIF2 > +#define CONFIG_SCIF_USE_EXT_CLK > + > +/* FLASH */ > +#define CONFIG_SPI > +#define CONFIG_SPI_FLASH_BAR > +#define CONFIG_SH_QSPI > +#define CONFIG_SPI_FLASH > +#define CONFIG_SPI_FLASH_SPANSION > +#define CONFIG_SPI_FLASH_QUAD > +#define CONFIG_SYS_NO_FLASH > + > +/* SH Ether */ > +#define CONFIG_NET_MULTI > +#define CONFIG_SH_ETHER > +#define CONFIG_SH_ETHER_USE_PORT 0 > +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 > +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII > +#define CONFIG_SH_ETHER_CACHE_WRITEBACK > +#define CONFIG_SH_ETHER_CACHE_INVALIDATE > +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 > +#define CONFIG_PHYLIB > +#define CONFIG_PHY_MICREL > +#define CONFIG_BITBANGMII > +#define CONFIG_BITBANGMII_MULTI > + > +/* Board Clock */ > +#define RMOBILE_XTAL_CLK 20000000u > +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK > +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ > +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) > +#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) > +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ > + > +#define CONFIG_SYS_TMU_CLK_DIV 4 > + > +/* i2c */ > +#define CONFIG_CMD_I2C > +#define CONFIG_SYS_I2C > +#define CONFIG_SYS_I2C_SH > +#define CONFIG_SYS_I2C_SLAVE 0x7F > +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 > +#define CONFIG_SYS_I2C_SH_SPEED0 400000 > +#define CONFIG_SYS_I2C_SH_SPEED1 400000 > +#define CONFIG_SYS_I2C_SH_SPEED2 400000 > +#define CONFIG_SH_I2C_DATA_HIGH 4 > +#define CONFIG_SH_I2C_DATA_LOW 5 > +#define CONFIG_SH_I2C_CLOCK 10000000 > + > +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ > + > +/* USB */ > +#define CONFIG_USB_STORAGE > +#define CONFIG_USB_EHCI > +#define CONFIG_USB_EHCI_RMOBILE > +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 > + > +/* MMCIF */ > +#define CONFIG_MMC > +#define CONFIG_GENERIC_MMC > +#define CONFIG_CMD_MMC > +#define CONFIG_SH_MMCIF > +#define CONFIG_SH_MMCIF_ADDR 0xee200000 > +#define CONFIG_SH_MMCIF_CLK 48000000 > + > +/* Module stop status bits */ > +/* INTC-RT */ > +#define CONFIG_SMSTP0_ENA 0x00400000 > +/* MSIF */ > +#define CONFIG_SMSTP2_ENA 0x00002000 > +/* INTC-SYS, IRQC */ > +#define CONFIG_SMSTP4_ENA 0x00000180 > +/* SCIF2 */ > +#define CONFIG_SMSTP7_ENA 0x00080000 > + > +#endif /* __SILK_H */ > -- > 1.9.1 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot
Hi Nobuhiro, I apologize for missed qos.h header file in this commit. Please do find it in upcoming patch. Regards, Vladimir On 06.02.2015 08:10, Nobuhiro Iwamatsu wrote: > Hi, Vladimir. > > Applied, thanks. > > Best regards, > Nobuhiro > > 2015-01-13 1:17 GMT+09:00 Vladimir Barinov > <vladimir.barinov@cogentembedded.com>: >> SILK is an entry level development board based on R-Car E2 SoC (R8A7794) >> >> This commit supports the following peripherals: >> - SCIF, I2C, Ethernet, QSPI, MMC, USB Host >> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> >> --- >> arch/arm/cpu/armv7/rmobile/Kconfig | 6 +- >> board/renesas/silk/Kconfig | 12 + >> board/renesas/silk/MAINTAINERS | 6 + >> board/renesas/silk/Makefile | 10 + >> board/renesas/silk/qos.c | 951 +++++++++++++++++++++++++++++++++++++ >> board/renesas/silk/silk.c | 175 +++++++ >> configs/silk_defconfig | 3 + >> include/configs/silk.h | 117 +++++ >> 8 files changed, 1279 insertions(+), 1 deletion(-) >> create mode 100644 board/renesas/silk/Kconfig >> create mode 100644 board/renesas/silk/MAINTAINERS >> create mode 100644 board/renesas/silk/Makefile >> create mode 100644 board/renesas/silk/qos.c >> create mode 100644 board/renesas/silk/silk.c >> create mode 100644 configs/silk_defconfig >> create mode 100644 include/configs/silk.h >>
Hi, 2015-02-09 9:18 GMT+09:00 Vladimir Barinov <vladimir.barinov@cogentembedded.com>: > Hi Nobuhiro, > > I apologize for missed qos.h header file in this commit. > Please do find it in upcoming patch. Yes, I noticed that the build test has failed now. I will wait for the patch. Thanks! Nobuhiro > > Regards, > Vladimir > > > On 06.02.2015 08:10, Nobuhiro Iwamatsu wrote: >> >> Hi, Vladimir. >> >> Applied, thanks. >> >> Best regards, >> Nobuhiro >> >> 2015-01-13 1:17 GMT+09:00 Vladimir Barinov >> <vladimir.barinov@cogentembedded.com>: >>> >>> SILK is an entry level development board based on R-Car E2 SoC (R8A7794) >>> >>> This commit supports the following peripherals: >>> - SCIF, I2C, Ethernet, QSPI, MMC, USB Host >>> >>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> >>> --- >>> arch/arm/cpu/armv7/rmobile/Kconfig | 6 +- >>> board/renesas/silk/Kconfig | 12 + >>> board/renesas/silk/MAINTAINERS | 6 + >>> board/renesas/silk/Makefile | 10 + >>> board/renesas/silk/qos.c | 951 >>> +++++++++++++++++++++++++++++++++++++ >>> board/renesas/silk/silk.c | 175 +++++++ >>> configs/silk_defconfig | 3 + >>> include/configs/silk.h | 117 +++++ >>> 8 files changed, 1279 insertions(+), 1 deletion(-) >>> create mode 100644 board/renesas/silk/Kconfig >>> create mode 100644 board/renesas/silk/MAINTAINERS >>> create mode 100644 board/renesas/silk/Makefile >>> create mode 100644 board/renesas/silk/qos.c >>> create mode 100644 board/renesas/silk/silk.c >>> create mode 100644 configs/silk_defconfig >>> create mode 100644 include/configs/silk.h >>> > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig index 6d94199..3586650 100644 --- a/arch/arm/cpu/armv7/rmobile/Kconfig +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -21,6 +21,9 @@ config TARGET_KZM9G config TARGET_ALT bool "Alt board" +config TARGET_SILK + bool "Silk board" + endchoice config SYS_SOC @@ -28,7 +31,7 @@ config SYS_SOC config RMOBILE_EXTRAM_BOOT bool "Enable boot from RAM" - depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER + depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK default n source "board/atmark-techno/armadillo-800eva/Kconfig" @@ -37,5 +40,6 @@ source "board/renesas/koelsch/Kconfig" source "board/renesas/lager/Kconfig" source "board/kmc/kzm9g/Kconfig" source "board/renesas/alt/Kconfig" +source "board/renesas/silk/Kconfig" endif diff --git a/board/renesas/silk/Kconfig b/board/renesas/silk/Kconfig new file mode 100644 index 0000000..07aee0e --- /dev/null +++ b/board/renesas/silk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SILK + +config SYS_BOARD + default "silk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "silk" + +endif diff --git a/board/renesas/silk/MAINTAINERS b/board/renesas/silk/MAINTAINERS new file mode 100644 index 0000000..b566ccf --- /dev/null +++ b/board/renesas/silk/MAINTAINERS @@ -0,0 +1,6 @@ +SILK BOARD +M: Cogent Embedded, Inc. <source@cogentembedded.com> +S: Maintained +F: board/renesas/silk/ +F: include/configs/silk.h +F: configs/silk_defconfig diff --git a/board/renesas/silk/Makefile b/board/renesas/silk/Makefile new file mode 100644 index 0000000..e6eea61 --- /dev/null +++ b/board/renesas/silk/Makefile @@ -0,0 +1,10 @@ +# +# board/renesas/silk/Makefile +# +# Copyright (C) 2015 Renesas Electronics Corporation +# Copyright (C) 2015 Cogent Embedded, Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := silk.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/silk/qos.c b/board/renesas/silk/qos.c new file mode 100644 index 0000000..4f6e46c --- /dev/null +++ b/board/renesas/silk/qos.c @@ -0,0 +1,951 @@ +/* + * board/renesas/silk/qos.c + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <asm/arch/rmobile.h> + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +/* QoS version 0.11 */ + +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +void qos_init(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x1F0D0B0A, &s3c->s3crorr); + writel(0x1F0D0B09, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x80928092, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x0000202A, &qos_addr->dbtmval2); + writel(0x00001FBD, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002019, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x00002043, &qos_addr->dbtmval2); + writel(0x00002030, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002031, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20000800, CCI_400_MAXOT_1); + writel(0x20000800, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00780080, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000E, &mxi_qos->du0); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +void qos_init(void) +{ +} +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c new file mode 100644 index 0000000..8818211 --- /dev/null +++ b/board/renesas/silk/silk.c @@ -0,0 +1,175 @@ +/* + * board/renesas/silk/silk.c + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/mmc.h> +#include <netdev.h> +#include <miiphy.h> +#include <i2c.h> +#include <div64.h> +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* QoS */ + qos_init(); + +#ifndef CONFIG_DCACHE_OFF + /* + * The caches are disabled when ACTLR.SMP is set to 0 + * regardless of the value of the SCTLR.C (cache enable bit) + * on Cortex-A7 MPCore + */ + asm volatile( + "mrc 15, 0, r0, c1, c0, 1\n" /* read ACTLR */ + "orr r0, r0, #(1 << 6)\n" /* set ACTLR.SMP bit */ + "mcr p15, 0, r0, c1, c0, 1\n"); /* write ACTLR */ +#endif +} + +#define TMU0_MSTP125 (1 << 25) +#define SCIF2_MSTP719 (1 << 19) +#define ETHER_MSTP813 (1 << 13) +#define IIC1_MSTP323 (1 << 23) +#define MMC0_MSTP315 (1 << 15) + +int board_early_init_f(void) +{ + /* TMU */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + /* SCIF2 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); + + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + + /* IIC1 / sh-i2c ch1 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); + +#ifdef CONFIG_SH_MMCIF + /* MMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); +#endif + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7794_pinmux_init(); + + /* Ether Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_MAGIC, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ8, NULL); + + /* PHY reset */ + gpio_request(GPIO_GP_1_24, NULL); + gpio_direction_output(GPIO_GP_1_24, 0); + mdelay(20); + gpio_set_value(GPIO_GP_1_24, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SH_ETHER + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + + return ret; +#else + return 0; +#endif +} + +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + +#ifdef CONFIG_SH_MMCIF + /* MMC0 */ + gpio_request(GPIO_GP_4_31, NULL); + gpio_set_value(GPIO_GP_4_31, 1); + + ret = mmcif_mmc_init(); +#endif + return ret; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(1); /* PowerIC connected to ch1 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} diff --git a/configs/silk_defconfig b/configs/silk_defconfig new file mode 100644 index 0000000..515ee33 --- /dev/null +++ b/configs/silk_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_RMOBILE=y +CONFIG_TARGET_SILK=y diff --git a/include/configs/silk.h b/include/configs/silk.h new file mode 100644 index 0000000..a4235e9 --- /dev/null +++ b/include/configs/silk.h @@ -0,0 +1,117 @@ +/* + * include/configs/silk.h + * This file is silk board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __SILK_H +#define __SILK_H + +#undef DEBUG +#define CONFIG_R8A7794 +#define CONFIG_RMOBILE_BOARD_STRING "Silk" + +#include "rcar-gen2-common.h" + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC +#endif +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF2 +#define CONFIG_SCIF_USE_EXT_CLK + +/* FLASH */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_QUAD +#define CONFIG_SYS_NO_FLASH + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) +#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* i2c */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* USB */ +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* MMCIF */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SH_MMCIF +#define CONFIG_SH_MMCIF_ADDR 0xee200000 +#define CONFIG_SH_MMCIF_CLK 48000000 + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF2 */ +#define CONFIG_SMSTP7_ENA 0x00080000 + +#endif /* __SILK_H */
SILK is an entry level development board based on R-Car E2 SoC (R8A7794) This commit supports the following peripherals: - SCIF, I2C, Ethernet, QSPI, MMC, USB Host Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> --- arch/arm/cpu/armv7/rmobile/Kconfig | 6 +- board/renesas/silk/Kconfig | 12 + board/renesas/silk/MAINTAINERS | 6 + board/renesas/silk/Makefile | 10 + board/renesas/silk/qos.c | 951 +++++++++++++++++++++++++++++++++++++ board/renesas/silk/silk.c | 175 +++++++ configs/silk_defconfig | 3 + include/configs/silk.h | 117 +++++ 8 files changed, 1279 insertions(+), 1 deletion(-) create mode 100644 board/renesas/silk/Kconfig create mode 100644 board/renesas/silk/MAINTAINERS create mode 100644 board/renesas/silk/Makefile create mode 100644 board/renesas/silk/qos.c create mode 100644 board/renesas/silk/silk.c create mode 100644 configs/silk_defconfig create mode 100644 include/configs/silk.h