Patchwork [2.6.32.3] ahci: AHCI and RAID mode SATA patch for Intel Cougar Point DeviceIDs

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Submitter Seth Heasley
Date Jan. 13, 2010, 1 a.m.
Message ID <201001121700.18234.seth.heasley@intel.com>
Download mbox | patch
Permalink /patch/42780/
State Not Applicable
Delegated to: David Miller
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Comments

Seth Heasley - Jan. 13, 2010, 1 a.m.
This patch adds the Intel Cougar Point (PCH) SATA AHCI and RAID Controller DeviceIDs.

Signed-off-by: Seth Heasley <seth.heasley@intel.com>

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Robert Hancock - Jan. 13, 2010, 4:40 a.m.
On 01/12/2010 07:00 PM, Seth Heasley wrote:
> This patch adds the Intel Cougar Point (PCH) SATA AHCI and RAID Controller DeviceIDs.
>
> Signed-off-by: Seth Heasley<seth.heasley@intel.com>
>
> --- linux-2.6.32.3/drivers/ata/ahci.c.orig	2010-01-06 15:07:45.000000000 -0800
> +++ linux-2.6.32.3/drivers/ata/ahci.c	2010-01-07 13:55:23.000000000 -0800
> @@ -560,6 +560,12 @@
>   	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
>   	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
>   	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
> +	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
> +	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
> +	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
> +	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
> +	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
> +	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
>
>   	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
>   	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,

The RAID mode entries would be needed if the device indicates RAID class 
in that mode, but in plain AHCI mode it should indicate SATA AHCI class 
which will get picked up by this catch-all so those entries shouldn't be 
needed:

         /* Generic, PCI class code for AHCI */
         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
           PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },

Likely a lot of the existing specific PCI IDs could be removed from the 
driver because of this (many likely predate the addition of the 
class-based catch-all). The only reason to need a specific entry if the 
device uses AHCI class is if it needs special handling or workarounds, 
which isn't the case here.
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Jeff Garzik - Jan. 13, 2010, 11:11 a.m.
On 01/12/2010 11:40 PM, Robert Hancock wrote:
> On 01/12/2010 07:00 PM, Seth Heasley wrote:
>> This patch adds the Intel Cougar Point (PCH) SATA AHCI and RAID
>> Controller DeviceIDs.
>>
>> Signed-off-by: Seth Heasley<seth.heasley@intel.com>
>>
>> --- linux-2.6.32.3/drivers/ata/ahci.c.orig 2010-01-06
>> 15:07:45.000000000 -0800
>> +++ linux-2.6.32.3/drivers/ata/ahci.c 2010-01-07 13:55:23.000000000 -0800
>> @@ -560,6 +560,12 @@
>> { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
>> { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
>> { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
>> + { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
>> + { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
>> + { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
>> + { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
>> + { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
>> + { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
>>
>> /* JMicron 360/1/3/5/6, match class to avoid IDE function */
>> { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
>
> The RAID mode entries would be needed if the device indicates RAID class
> in that mode, but in plain AHCI mode it should indicate SATA AHCI class
> which will get picked up by this catch-all so those entries shouldn't be
> needed:
>
> /* Generic, PCI class code for AHCI */
> { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
> PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
>
> Likely a lot of the existing specific PCI IDs could be removed from the
> driver because of this (many likely predate the addition of the
> class-based catch-all). The only reason to need a specific entry if the
> device uses AHCI class is if it needs special handling or workarounds,
> which isn't the case here.

Well, two lines of thinking here:

* some of lines of Intel chips do not separate AHCI into a separate PCI 
ID rather legacy IDE interface.  When an AHCI interface exists and 
AHCI/IDE share the same PCI ID, we default to using AHCI.  Thus, some of 
those PCI ID matches in ahci.c's PCI table may not get caught by the 
generic PCI class match at the end of the table.

* the cost carrying redundant PCI IDs seems low, harmless, and 
potentially helpful.

Comments welcome, though...

	Jeff




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David Milburn - Jan. 13, 2010, 2:59 p.m.
Jeff Garzik wrote:
> On 01/12/2010 11:40 PM, Robert Hancock wrote:
>> On 01/12/2010 07:00 PM, Seth Heasley wrote:
>>> This patch adds the Intel Cougar Point (PCH) SATA AHCI and RAID
>>> Controller DeviceIDs.
>>>
>>> Signed-off-by: Seth Heasley<seth.heasley@intel.com>
>>>
>>> --- linux-2.6.32.3/drivers/ata/ahci.c.orig 2010-01-06
>>> 15:07:45.000000000 -0800
>>> +++ linux-2.6.32.3/drivers/ata/ahci.c 2010-01-07 13:55:23.000000000 
>>> -0800
>>> @@ -560,6 +560,12 @@
>>> { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
>>> { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
>>> { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
>>> + { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
>>> + { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
>>> + { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
>>> + { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
>>> + { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
>>> + { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
>>>
>>> /* JMicron 360/1/3/5/6, match class to avoid IDE function */
>>> { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
>>
>> The RAID mode entries would be needed if the device indicates RAID class
>> in that mode, but in plain AHCI mode it should indicate SATA AHCI class
>> which will get picked up by this catch-all so those entries shouldn't be
>> needed:
>>
>> /* Generic, PCI class code for AHCI */
>> { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
>> PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
>>
>> Likely a lot of the existing specific PCI IDs could be removed from the
>> driver because of this (many likely predate the addition of the
>> class-based catch-all). The only reason to need a specific entry if the
>> device uses AHCI class is if it needs special handling or workarounds,
>> which isn't the case here.
> 
> Well, two lines of thinking here:
> 
> * some of lines of Intel chips do not separate AHCI into a separate PCI 
> ID rather legacy IDE interface.  When an AHCI interface exists and 
> AHCI/IDE share the same PCI ID, we default to using AHCI.  Thus, some of 
> those PCI ID matches in ahci.c's PCI table may not get caught by the 
> generic PCI class match at the end of the table.
> 
> * the cost carrying redundant PCI IDs seems low, harmless, and 
> potentially helpful.

It is helpful for the specific device IDs to show up in "modinfo ahci" and
modules.pcimap.

David

> 
> Comments welcome, though...
> 
>     Jeff
> 
> 
> 
> 
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Seth Heasley - Jan. 13, 2010, 3:43 p.m.
>> * some of lines of Intel chips do not separate AHCI into a separate PCI
>> ID rather legacy IDE interface.  When an AHCI interface exists and
>> AHCI/IDE share the same PCI ID, we default to using AHCI.  Thus, some of
>> those PCI ID matches in ahci.c's PCI table may not get caught by the
>> generic PCI class match at the end of the table.
>>
>> * the cost carrying redundant PCI IDs seems low, harmless, and
>> potentially helpful.
>
>It is helpful for the specific device IDs to show up in "modinfo ahci" and
>modules.pcimap.
>
>David

This is the reason I was asked to start adding the AHCI DeviceIDs here.

-Seth
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Robert Hancock - Jan. 14, 2010, 12:03 a.m.
On Wed, Jan 13, 2010 at 9:43 AM, Heasley, Seth <seth.heasley@intel.com> wrote:
>>> * some of lines of Intel chips do not separate AHCI into a separate PCI
>>> ID rather legacy IDE interface.  When an AHCI interface exists and
>>> AHCI/IDE share the same PCI ID, we default to using AHCI.  Thus, some of
>>> those PCI ID matches in ahci.c's PCI table may not get caught by the
>>> generic PCI class match at the end of the table.
>>>
>>> * the cost carrying redundant PCI IDs seems low, harmless, and
>>> potentially helpful.
>>
>>It is helpful for the specific device IDs to show up in "modinfo ahci" and
>>modules.pcimap.
>>
>>David
>
> This is the reason I was asked to start adding the AHCI DeviceIDs here.

I'm not sure why exactly that is useful - or at least why it's useful
enough to be worth the effort of patching the kernel for every new
AHCI controller that gets released..

I looked at what the Windows msahci driver is doing, they're not
listing any specific device IDs at all, they're just using the class
code matching only. (Of course, they don't have to worry about devices
in RAID mode, as those have to use vendor-specific drivers..)
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Robert Hancock - Jan. 14, 2010, 12:11 a.m.
On Wed, Jan 13, 2010 at 5:11 AM, Jeff Garzik <jgarzik@pobox.com> wrote:
>> Likely a lot of the existing specific PCI IDs could be removed from the
>> driver because of this (many likely predate the addition of the
>> class-based catch-all). The only reason to need a specific entry if the
>> device uses AHCI class is if it needs special handling or workarounds,
>> which isn't the case here.
>
> Well, two lines of thinking here:
>
> * some of lines of Intel chips do not separate AHCI into a separate PCI ID
> rather legacy IDE interface.  When an AHCI interface exists and AHCI/IDE
> share the same PCI ID, we default to using AHCI.  Thus, some of those PCI ID
> matches in ahci.c's PCI table may not get caught by the generic PCI class
> match at the end of the table.

Well, ata_piix does have a couple of entries that are listed in ahci
as well, for ICH6 device IDs 0x2652 and 0x2653. For 0x2653 ata_piix
checks the class code to make sure it's IDE, but for the 0x2652 entry,
and in both cases in ahci, the class code isn't checked. Deleting the
specific entries from ahci for those controllers would seemingly
actually improve the situation, since then ahci wouldn't try and
attach to those devices when they indicate IDE class. ata_piix should
also should be checking for IDE class on 0x2652 as well.
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Robert Hancock - Jan. 14, 2010, 12:42 a.m.
On Wed, Jan 13, 2010 at 6:11 PM, Robert Hancock <hancockrwd@gmail.com> wrote:
> On Wed, Jan 13, 2010 at 5:11 AM, Jeff Garzik <jgarzik@pobox.com> wrote:
>>> Likely a lot of the existing specific PCI IDs could be removed from the
>>> driver because of this (many likely predate the addition of the
>>> class-based catch-all). The only reason to need a specific entry if the
>>> device uses AHCI class is if it needs special handling or workarounds,
>>> which isn't the case here.
>>
>> Well, two lines of thinking here:
>>
>> * some of lines of Intel chips do not separate AHCI into a separate PCI ID
>> rather legacy IDE interface.  When an AHCI interface exists and AHCI/IDE
>> share the same PCI ID, we default to using AHCI.  Thus, some of those PCI ID
>> matches in ahci.c's PCI table may not get caught by the generic PCI class
>> match at the end of the table.
>
> Well, ata_piix does have a couple of entries that are listed in ahci
> as well, for ICH6 device IDs 0x2652 and 0x2653. For 0x2653 ata_piix
> checks the class code to make sure it's IDE, but for the 0x2652 entry,
> and in both cases in ahci, the class code isn't checked. Deleting the
> specific entries from ahci for those controllers would seemingly
> actually improve the situation, since then ahci wouldn't try and
> attach to those devices when they indicate IDE class. ata_piix should
> also should be checking for IDE class on 0x2652 as well.

Hmm, it seems like it's a bit more complicated than that. For ICH6R
(0x2652), ata_piix attaches to it regardless of mode intentionally, it
has specific logic to disable AHCI on the controller since it can be
used in either mode. That seems a bit questionable. Having the same
device being handled by different enabled drivers and depending on
link or module load order to decide which one loads is fragile and
prone to errors. I'd be in favor of removing the ICH6R support from
ata_piix entirely and saying that you should be using ahci for that
device. Maybe when ahci was immature there was a benefit to allowing
ata_piix to run it, but I doubt that's true today.
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Krzysztof Halasa - Jan. 14, 2010, 3:40 p.m.
Robert Hancock <hancockrwd@gmail.com> writes:

> Well, ata_piix does have a couple of entries that are listed in ahci
> as well, for ICH6 device IDs 0x2652 and 0x2653. For 0x2653 ata_piix
> checks the class code to make sure it's IDE, but for the 0x2652 entry,
> and in both cases in ahci, the class code isn't checked. Deleting the
> specific entries from ahci for those controllers would seemingly
> actually improve the situation, since then ahci wouldn't try and
> attach to those devices when they indicate IDE class. ata_piix should
> also should be checking for IDE class on 0x2652 as well.

Interestingly the ICH6* datasheet says:
2651 is plain ICH6 (not RAID/AHCI capable)
2652 is ICH6R
2553 is ICH6-M

The subclass code is:
for plain ICH6: 01 (IDE controller)
for ICH6R: 04 (RAID controller)
for ICH6-M: 01 (IDE) or 06 (SATA=AHCI)

I think later chips change their subclass depending on
IDE/AHCI/RAID BIOS setting, wasn't it the ICH6R case as well?

Not checking the subclass for ICH6-M in ahci driver may be a bug,
unless ahci can handle the chip in BIOS-set IDE mode. Not checking
ICH6R code (or checking only for RAID) seems right, though.
Henrique de Moraes Holschuh - Jan. 14, 2010, 8:11 p.m.
On Wed, 13 Jan 2010, Robert Hancock wrote:
> Hmm, it seems like it's a bit more complicated than that. For ICH6R
> (0x2652), ata_piix attaches to it regardless of mode intentionally, it
> has specific logic to disable AHCI on the controller since it can be
> used in either mode. That seems a bit questionable. Having the same
> device being handled by different enabled drivers and depending on
> link or module load order to decide which one loads is fragile and
> prone to errors. I'd be in favor of removing the ICH6R support from
> ata_piix entirely and saying that you should be using ahci for that
> device. Maybe when ahci was immature there was a benefit to allowing
> ata_piix to run it, but I doubt that's true today.

Maybe it is the silicon AHCI in ICH6R that is immature, and one is much
better of using it in IDE mode?
Robert Hancock - Jan. 15, 2010, 12:15 a.m.
On Thu, Jan 14, 2010 at 2:11 PM, Henrique de Moraes Holschuh
<hmh@hmh.eng.br> wrote:
> On Wed, 13 Jan 2010, Robert Hancock wrote:
>> Hmm, it seems like it's a bit more complicated than that. For ICH6R
>> (0x2652), ata_piix attaches to it regardless of mode intentionally, it
>> has specific logic to disable AHCI on the controller since it can be
>> used in either mode. That seems a bit questionable. Having the same
>> device being handled by different enabled drivers and depending on
>> link or module load order to decide which one loads is fragile and
>> prone to errors. I'd be in favor of removing the ICH6R support from
>> ata_piix entirely and saying that you should be using ahci for that
>> device. Maybe when ahci was immature there was a benefit to allowing
>> ata_piix to run it, but I doubt that's true today.
>
> Maybe it is the silicon AHCI in ICH6R that is immature, and one is much
> better of using it in IDE mode?

That seems unlikely, since the Intel-provided Matrix Storage drivers
for that controller on Windows will be using AHCI mode..
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Henrique de Moraes Holschuh - Jan. 16, 2010, 3:02 a.m.
On Thu, 14 Jan 2010, Robert Hancock wrote:
> > Maybe it is the silicon AHCI in ICH6R that is immature, and one is much
> > better of using it in IDE mode?
> 
> That seems unlikely, since the Intel-provided Matrix Storage drivers
> for that controller on Windows will be using AHCI mode..

That doesn't say much.

If the change doesn't risk switching unaware users from IDE mode to AHCI, it
is not a problem.  But if it does, why risk it?  It is not like anyone that
wants hotplug and has an ICH6-R/M system won't have figured it out by now
how to get it to use AHCI, these are NOT new systems.

AHCI in ICH6R or ICH6M is not always an advantage.  You don't want it on
ICH6-M in a laptop if it is not going to use the hotplug, for example.  In
AHCI mode, the chip draws more power.
Robert Hancock - Jan. 16, 2010, 4:57 a.m.
On Fri, Jan 15, 2010 at 9:02 PM, Henrique de Moraes Holschuh
<hmh@hmh.eng.br> wrote:
> On Thu, 14 Jan 2010, Robert Hancock wrote:
>> > Maybe it is the silicon AHCI in ICH6R that is immature, and one is much
>> > better of using it in IDE mode?
>>
>> That seems unlikely, since the Intel-provided Matrix Storage drivers
>> for that controller on Windows will be using AHCI mode..
>
> That doesn't say much.
>
> If the change doesn't risk switching unaware users from IDE mode to AHCI, it
> is not a problem.  But if it does, why risk it?  It is not like anyone that
> wants hotplug and has an ICH6-R/M system won't have figured it out by now
> how to get it to use AHCI, these are NOT new systems.
>
> AHCI in ICH6R or ICH6M is not always an advantage.  You don't want it on
> ICH6-M in a laptop if it is not going to use the hotplug, for example.  In
> AHCI mode, the chip draws more power.

Well, the ICH6M seems to be stuck in whatever mode the user and/or
BIOS designer has stuck it in,so nothing would change with it, only
with the ICH6R which is not a mobile chipset. I'm not sure about using
more power in the controller in AHCI mode, but in IDE mode, you can't
use SATA link power saving, which is likely just as significant.
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Tejun Heo - Jan. 20, 2010, 3:21 a.m.
On 01/15/2010 09:15 AM, Robert Hancock wrote:
> On Thu, Jan 14, 2010 at 2:11 PM, Henrique de Moraes Holschuh
> <hmh@hmh.eng.br> wrote:
>> On Wed, 13 Jan 2010, Robert Hancock wrote:
>>> Hmm, it seems like it's a bit more complicated than that. For ICH6R
>>> (0x2652), ata_piix attaches to it regardless of mode intentionally, it
>>> has specific logic to disable AHCI on the controller since it can be
>>> used in either mode. That seems a bit questionable. Having the same
>>> device being handled by different enabled drivers and depending on
>>> link or module load order to decide which one loads is fragile and
>>> prone to errors. I'd be in favor of removing the ICH6R support from
>>> ata_piix entirely and saying that you should be using ahci for that
>>> device. Maybe when ahci was immature there was a benefit to allowing
>>> ata_piix to run it, but I doubt that's true today.
>>
>> Maybe it is the silicon AHCI in ICH6R that is immature, and one is much
>> better of using it in IDE mode?
> 
> That seems unlikely, since the Intel-provided Matrix Storage drivers
> for that controller on Windows will be using AHCI mode..

Oh, some ich6 ahcis are very not very mature.  I have a ich6 which can
do ATA in ahci mode fine but craps out on ATAPI (it ends up spitting
out garbage FISes on the wire).  It works fine in piix mode.
ich6 is a dying strange beast.

Thanks.
Jeff Garzik - Jan. 20, 2010, 7:28 p.m.
On 01/12/2010 08:00 PM, Seth Heasley wrote:
> This patch adds the Intel Cougar Point (PCH) SATA AHCI and RAID Controller DeviceIDs.
>
> Signed-off-by: Seth Heasley<seth.heasley@intel.com>
>
> --- linux-2.6.32.3/drivers/ata/ahci.c.orig	2010-01-06 15:07:45.000000000 -0800
> +++ linux-2.6.32.3/drivers/ata/ahci.c	2010-01-07 13:55:23.000000000 -0800
> @@ -560,6 +560,12 @@
>   	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
>   	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
>   	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
> +	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
> +	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
> +	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
> +	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
> +	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
> +	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */

applied this, and the ata_piix patch


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Patch

--- linux-2.6.32.3/drivers/ata/ahci.c.orig	2010-01-06 15:07:45.000000000 -0800
+++ linux-2.6.32.3/drivers/ata/ahci.c	2010-01-07 13:55:23.000000000 -0800
@@ -560,6 +560,12 @@ 
 	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
 	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
 	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
+	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
+	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
+	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
 
 	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
 	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,