| Message ID | 1421052378-29913-3-git-send-email-B37916@freescale.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Stefano Babic |
| Headers | show |
Hi Ye, On 12/01/2015 09:46, Ye.Li wrote: > On mx6sx, the CCM register bits for GPMI are different as other > mx6 platforms. Modify the GPMI clock function to support mx6sx. > > Signed-off-by: Ye.Li <B37916@freescale.com> > --- > arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++ > 1 files changed, 12 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c > index fd57f22..ce7f0f7 100644 > --- a/arch/arm/cpu/armv7/mx6/clock.c > +++ b/arch/arm/cpu/armv7/mx6/clock.c > @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg) > MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | > MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); > > +#if defined(CONFIG_MX6SX) > + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); > + > + clrsetbits_le32(&imx_ccm->cs2cdr, > + MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | > + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | > + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK, > + cfg); > + > + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); > +#els If I have well understood, this code is protected by CONFIG_NAND_MXS, and that conflicts with what you are willing to do (setting clocks for QSPI). I suggest to split setup_gpmi_io_clk() function, that at the moment is ony for NAND, having something like: void setup_gpmi_io_clk() { #ifdef CONFIG_NAND_MXS ...setup nand #endif ...setup qspi } Best regards, Stefano Babic
Hi Stefano, On 2/10/2015 6:26 PM, Stefano Babic wrote: > Hi Ye, > > On 12/01/2015 09:46, Ye.Li wrote: >> On mx6sx, the CCM register bits for GPMI are different as other >> mx6 platforms. Modify the GPMI clock function to support mx6sx. >> >> Signed-off-by: Ye.Li <B37916@freescale.com> >> --- >> arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++ >> 1 files changed, 12 insertions(+), 0 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c >> index fd57f22..ce7f0f7 100644 >> --- a/arch/arm/cpu/armv7/mx6/clock.c >> +++ b/arch/arm/cpu/armv7/mx6/clock.c >> @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg) >> MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | >> MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); >> >> +#if defined(CONFIG_MX6SX) >> + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); >> + >> + clrsetbits_le32(&imx_ccm->cs2cdr, >> + MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | >> + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | >> + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK, >> + cfg); >> + >> + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); >> +#els > If I have well understood, this code is protected by CONFIG_NAND_MXS, > and that conflicts with what you are willing to do (setting clocks for > QSPI). I suggest to split setup_gpmi_io_clk() function, that at the > moment is ony for NAND, having something like: > > void setup_gpmi_io_clk() > { > #ifdef CONFIG_NAND_MXS > > ...setup nand > #endif > > ...setup qspi > > } > > Best regards, > Stefano Babic > I feel you misunderstand the patch. On i.MX6sx, the QSPI2 and GPMI shares the same clock root of QSPI2. So you can see the register bits are named with "MXC_CCM_CS2CDR_QSPI2_xxx". Actually, not only the name, there is a little different in the CS2CDR register bits layout. The patch is used to fix the gap. Also the the GPMI pins are multiplexed with QSPI2 pins, so either NAND or QSPI2 can work, there is no conflict. Best regards, Ye Li
Hi Ye.Li, On 11/02/2015 04:14, Li Ye-B37916 wrote: >> > I feel you misunderstand the patch. Thanks for clarifications. > On i.MX6sx, the QSPI2 and GPMI shares the same clock root of QSPI2. So you can see the register bits are > named with "MXC_CCM_CS2CDR_QSPI2_xxx". Actually, not only the name, there is a little different in the CS2CDR register bits layout. The patch is used to fix the gap. > > Also the the GPMI pins are multiplexed with QSPI2 pins, so either NAND or QSPI2 can work, there is no conflict. Ok, understood - then it is fine with me. Best regards, Stefano Babic
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fd57f22..ce7f0f7 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg) MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); +#if defined(CONFIG_MX6SX) + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); + + clrsetbits_le32(&imx_ccm->cs2cdr, + MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK, + cfg); + + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); +#else clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); clrsetbits_le32(&imx_ccm->cs2cdr, @@ -56,6 +67,7 @@ void setup_gpmi_io_clk(u32 cfg) cfg); setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); +#endif setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx. Signed-off-by: Ye.Li <B37916@freescale.com> --- arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-)