From patchwork Wed Jan 7 15:20:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 426251 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C4AD51400B7 for ; Thu, 8 Jan 2015 02:21:48 +1100 (AEDT) Received: from localhost ([::1]:41141 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y8sQc-0007Hw-Qo for incoming@patchwork.ozlabs.org; Wed, 07 Jan 2015 10:21:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39902) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y8sPm-0005rn-9d for qemu-devel@nongnu.org; Wed, 07 Jan 2015 10:20:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y8sPk-0003DU-7K for qemu-devel@nongnu.org; Wed, 07 Jan 2015 10:20:54 -0500 Received: from cantor2.suse.de ([195.135.220.15]:37825 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y8sPj-0003A2-8f; Wed, 07 Jan 2015 10:20:51 -0500 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 3C1177501C; Wed, 7 Jan 2015 15:20:50 +0000 (UTC) From: Alexander Graf To: qemu-ppc@nongnu.org Date: Wed, 7 Jan 2015 16:20:33 +0100 Message-Id: <1420644048-16919-23-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1420644048-16919-1-git-send-email-agraf@suse.de> References: <1420644048-16919-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 195.135.220.15 Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Tom Musta Subject: [Qemu-devel] [PULL 22/37] target-ppc: Introduce tm_enabled Bit to CPU State X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Tom Musta Add a bit (tm_enabled) to CPU state that mirrors the MSR[TM] bit. This is analogous to the other "available" bits in the MSR (FP, VSX, etc.). NOTE: Since MSR[TM] occupies big-endian bit 31, the code is wrapped with a PPC64 bit check. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/translate.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index a772382..3b004f3 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -203,6 +203,7 @@ typedef struct DisasContext { int altivec_enabled; int vsx_enabled; int spe_enabled; + int tm_enabled; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint64_t insns_flags; @@ -11342,6 +11343,13 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, } else { ctx.vsx_enabled = 0; } +#if defined(TARGET_PPC64) + if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { + ctx.tm_enabled = msr_tm; + } else { + ctx.tm_enabled = 0; + } +#endif if ((env->flags & POWERPC_FLAG_SE) && msr_se) ctx.singlestep_enabled = CPU_SINGLE_STEP; else