From patchwork Thu Jan 7 20:28:21 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [6/9] sparc64: add macros to deal with softint and timer interrupt From: "Igor V. Kovalenko" X-Patchwork-Id: 42475 Message-Id: <20100107202820.16653.91025.stgit@skyserv> To: qemu-devel@nongnu.org Date: Thu, 07 Jan 2010 23:28:21 +0300 From: Igor V. Kovalenko Signed-off-by: Igor V. Kovalenko --- hw/sun4u.c | 1 - target-sparc/cpu.h | 4 ++++ 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/hw/sun4u.c b/hw/sun4u.c index 9d46f08..029e3ed 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -73,7 +73,6 @@ #define MAX_PILS 16 -#define TICK_INT_DIS 0x8000000000000000ULL #define TICK_MAX 0x7fffffffffffffffULL struct hwdef { diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 1fe4d0f..0f0e38c 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -394,6 +394,8 @@ typedef struct CPUSPARCState { uint64_t fprs; uint64_t tick_cmpr, stick_cmpr; void *tick, *stick; +#define TICK_NPT_MASK 0x8000000000000000ULL +#define TICK_INT_DIS 0x8000000000000000ULL uint64_t gsr; uint32_t gl; // UA2005 /* UA 2005 hyperprivileged registers */ @@ -402,6 +404,8 @@ typedef struct CPUSPARCState { uint32_t softint; #define SOFTINT_TIMER 1 #define SOFTINT_STIMER (1 << 16) +#define SOFTINT_INTRMASK (0xFFFE) +#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) #endif sparc_def_t *def; } CPUSPARCState;