Patchwork Fix 2.6.33rc1 regression in et131x

login
register
mail settings
Submitter Alan Cox
Date Jan. 6, 2010, 2:01 p.m.
Message ID <20100106140126.6f26ddde@lxorguk.ukuu.org.uk>
Download mbox | patch
Permalink /patch/42292/
State Not Applicable
Delegated to: David Miller
Headers show

Comments

Alan Cox - Jan. 6, 2010, 2:01 p.m.
et131x: Fix 12bit wrapping

From: Alan Cox <alan@linux.intel.com>

The 12bit wrap logic conversion is wrong and this shows up for some
memory sizes and layouts of card. Patch it up for now, once the kernel
view of status is cleaned up it'll become two variables and a lot saner.

Signed-off-by: Alan Cox <alan@linux.intel.com>
---

 drivers/staging/et131x/et1310_address_map.h |   18 +++++++++++++-----
 drivers/staging/et131x/et1310_rx.c          |    6 +++---
 2 files changed, 16 insertions(+), 8 deletions(-)


--
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Patch

diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h
index 6da843c..e715e4d 100644
--- a/drivers/staging/et131x/et1310_address_map.h
+++ b/drivers/staging/et131x/et1310_address_map.h
@@ -203,11 +203,14 @@  typedef struct _GLOBAL_t {			/* Location: */
  * 9-0: pr ndes
  */
 
-#define ET_DMA10_MASK		0x3FF	/* 10 bit mask for DMA10W types */
-#define ET_DMA10_WRAP		0x400
-#define ET_DMA4_MASK		0x00F	/* 4 bit mask for DMA4W types */
-#define ET_DMA4_WRAP		0x010
-
+#define ET_DMA12_MASK		0x0FFF	/* 12 bit mask for DMA12W types */
+#define ET_DMA12_WRAP		0x1000
+#define ET_DMA10_MASK		0x03FF	/* 10 bit mask for DMA10W types */
+#define ET_DMA10_WRAP		0x0400
+#define ET_DMA4_MASK		0x000F	/* 4 bit mask for DMA4W types */
+#define ET_DMA4_WRAP		0x0010
+
+#define INDEX12(x)	((x) & ET_DMA12_MASK)
 #define INDEX10(x)	((x) & ET_DMA10_MASK)
 #define INDEX4(x)	((x) & ET_DMA4_MASK)
 
@@ -216,6 +219,11 @@  extern inline void add_10bit(u32 *v, int n)
 	*v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
 }
 
+extern inline void add_12bit(u32 *v, int n)
+{
+	*v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
+}
+
 /*
  * 10bit DMA with wrap
  * txdma tx queue write address reg in txdma address map at 0x1010
diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c
index 3ddc9b1..81c1a74 100644
--- a/drivers/staging/et131x/et1310_rx.c
+++ b/drivers/staging/et131x/et1310_rx.c
@@ -831,10 +831,10 @@  PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
 
 	/* Indicate that we have used this PSR entry. */
 	/* FIXME wrap 12 */
-	rx_local->local_psr_full = (rx_local->local_psr_full + 1) & 0xFFF;
-	if (rx_local->local_psr_full  > rx_local->PsrNumEntries - 1) {
+	add_12bit(&rx_local->local_psr_full, 1);
+	if ((rx_local->local_psr_full & 0xFFF)  > rx_local->PsrNumEntries - 1) {
 		/* Clear psr full and toggle the wrap bit */
-		rx_local->local_psr_full &=  0xFFF;
+		rx_local->local_psr_full &=  ~0xFFF;
 		rx_local->local_psr_full ^= 0x1000;
 	}