diff mbox

[2/2,ARM] : New CPU support for Marvell Whitney

Message ID 5493DF85.6050309@marvell.com
State New
Headers show

Commit Message

Xingxing Pan Dec. 19, 2014, 8:19 a.m. UTC 
Hi,

This patch expands the arm types neon_logic<q>, neon_from_gp<q> and
neon_to_gp<q>. This change mainly suits to marvell-whitney cores, and
will not affect other arm core's pipeline description.

neon_logic<q> is expanded to neon_logic_reg<q> and neon_logic_imm<q>,
corresponding respectively to the predicates s_register_operand and
imm_for_neon_logic_operand.

neon_from/to_gp<q> is expanded to neon_reg_from/to_gp<q> and
neon_lane_from/to_gp<q>, decided by whether the neon side is a single
register or a register lane.

Test on linux-gnueabi and no new regressions are found. OK for trunk?

Regards,
Xingxing


        2014-12-19  Xingxing Pan  <xxingpan@marvell.com>

            * config/arm/types.md:
            (neon_logic): Expand to neon_logic_reg and neon_logic_imm.
            (neon_logic_q): Expand to neon_logic_reg_q and neon_logic_imm_q.
            (neon_from_gp): Expand to neon_reg_from_gp and 
neon_lane_from_gp.
            (neon_from_gp_q): Expand to neon_reg_from_gp_q and
neon_lane_from_gp_q.
            (neon_to_gp): Expand to neon_reg_to_gp and neon_lane_to_gp.
            (neon_to_gp_q): Expand to neon_reg_to_gp_q and 
neon_lane_to_gp_q.
            * config/aarch64/aarch64-simd.md: Ditto.
            * config/aarch64/aarch64.md: Ditto.
            * config/aarch64/thunderx.md: Ditto.
            * config/arm/arm.md: Ditto.
            * config/arm/cortex-a15-neon.md: Ditto.
            * config/arm/cortex-a17-neon.md: Ditto.
            * config/arm/cortex-a8-neon.md: Ditto.
            * config/arm/cortex-a9-neon.md: Ditto.
            * config/arm/neon.md: Ditto.
            * config/arm/whitney.md: Ditto.

               neon_shift_imm_long, neon_shift_reg, neon_shift_reg_q,\
               neon_shift_acc, neon_shift_acc_q, neon_sat_shift_imm,\
@@ -1125,7 +1138,9 @@
               neon_sat_mla_b_long, neon_sat_mla_h_long,\
               neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\
               neon_sat_mla_s_scalar_long,\
-          neon_to_gp, neon_to_gp_q, neon_from_gp, neon_from_gp_q,\
+          neon_reg_to_gp, neon_reg_to_gp_q, neon_reg_from_gp,\
+          neon_reg_from_gp_q, neon_lane_to_gp, neon_lane_to_gp_q,\
+          neon_lane_from_gp, neon_lane_from_gp_q,\
               neon_ldr, neon_load1_1reg, neon_load1_1reg_q,
neon_load1_2reg,\
               neon_load1_2reg_q, neon_load1_3reg, neon_load1_3reg_q,\
               neon_load1_4reg, neon_load1_4reg_q, neon_load1_all_lanes,\

Comments

James Greenhalgh Dec. 19, 2014, 9:35 a.m. UTC | #1 
On Fri, Dec 19, 2014 at 08:19:17AM +0000, Xingxing Pan wrote:
> Hi,
> 
> This patch expands the arm types neon_logic<q>, neon_from_gp<q> and
> neon_to_gp<q>. This change mainly suits to marvell-whitney cores, and
> will not affect other arm core's pipeline description.
> 
> neon_logic<q> is expanded to neon_logic_reg<q> and neon_logic_imm<q>,
> corresponding respectively to the predicates s_register_operand and
> imm_for_neon_logic_operand.
> 
> neon_from/to_gp<q> is expanded to neon_reg_from/to_gp<q> and
> neon_lane_from/to_gp<q>, decided by whether the neon side is a single
> register or a register lane.

Sorry to ask for churn here, but the naming scheme for lane operations
elsewhere in types.md seems to be:

neon_<operation><_scalar><_q>

as in:

; neon_mul_s_scalar
; neon_mul_s_scalar_q

I think the types you are introducing should be:

  neon_from_gp_scalar<q>
  neon_to_gp_scalar<q>
 
Thanks,
James
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index d4256a5..ea92940 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -49,7 +49,7 @@ 
       "@
        dup\\t%0.<Vtype>, %<vw>1
        dup\\t%0.<Vtype>, %1.<Vetype>[0]"
-  [(set_attr "type" "neon_from_gp<q>, neon_dup<q>")]
+  [(set_attr "type" "neon_reg_from_gp<q>, neon_dup<q>")]
     )

     (define_insn "aarch64_simd_dup<mode>"
@@ -115,7 +115,7 @@ 
          }
     }
       [(set_attr "type" "neon_load1_1reg<q>, neon_store1_1reg<q>,\
-                     neon_logic<q>, neon_to_gp<q>, neon_from_gp<q>,\
+                     neon_logic_reg<q>, neon_lane_to_gp<q>,
neon_lane_from_gp<q>,\
                          mov_reg, neon_move<q>")]
     )

@@ -147,7 +147,7 @@ 
         }
     }
       [(set_attr "type" "neon_load1_1reg<q>, neon_store1_1reg<q>,\
-                     neon_logic<q>, multiple, multiple, multiple,\
+                     neon_logic_reg<q>, multiple, multiple, multiple,\
                          neon_move<q>")
        (set_attr "length" "4,4,4,8,8,8,4")]
     )
@@ -227,7 +227,7 @@ 
               (match_operand:VQ 2 "vect_par_cnst_lo_half" "")))]
       "TARGET_SIMD && reload_completed"
       "umov\t%0, %1.d[0]"
-  [(set_attr "type" "neon_to_gp<q>")
+  [(set_attr "type" "neon_lane_to_gp<q>")
        (set_attr "length" "4")
       ])

@@ -238,7 +238,7 @@ 
               (match_operand:VQ 2 "vect_par_cnst_hi_half" "")))]
       "TARGET_SIMD && reload_completed"
       "umov\t%0, %1.d[1]"
-  [(set_attr "type" "neon_to_gp<q>")
+  [(set_attr "type" "neon_lane_to_gp<q>")
        (set_attr "length" "4")
       ])

@@ -248,7 +248,7 @@ 
                   (match_operand:VDQ_I 2 "register_operand" "w")))]
      "TARGET_SIMD"
      "orn\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
-  [(set_attr "type" "neon_logic<q>")]
+  [(set_attr "type" "neon_logic_reg<q>")]
     )

     (define_insn "bic<mode>3"
@@ -257,7 +257,7 @@ 
                   (match_operand:VDQ_I 2 "register_operand" "w")))]
      "TARGET_SIMD"
      "bic\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
-  [(set_attr "type" "neon_logic<q>")]
+  [(set_attr "type" "neon_logic_reg<q>")]
     )

     (define_insn "add<mode>3"
@@ -440,7 +440,7 @@ 
                    (match_operand:VDQ_I 2 "register_operand" "w")))]
       "TARGET_SIMD"
       "and\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
-  [(set_attr "type" "neon_logic<q>")]
+  [(set_attr "type" "neon_logic_reg<q>")]
     )

     (define_insn "ior<mode>3"
@@ -449,7 +449,7 @@ 
                    (match_operand:VDQ_I 2 "register_operand" "w")))]
       "TARGET_SIMD"
       "orr\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
-  [(set_attr "type" "neon_logic<q>")]
+  [(set_attr "type" "neon_logic_reg<q>")]
     )

     (define_insn "xor<mode>3"
@@ -458,7 +458,7 @@ 
                    (match_operand:VDQ_I 2 "register_operand" "w")))]
       "TARGET_SIMD"
       "eor\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
-  [(set_attr "type" "neon_logic<q>")]
+  [(set_attr "type" "neon_logic_reg<q>")]
     )

     (define_insn "one_cmpl<mode>2"
@@ -466,7 +466,7 @@ 
             (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")))]
       "TARGET_SIMD"
       "not\t%0.<Vbtype>, %1.<Vbtype>"
-  [(set_attr "type" "neon_logic<q>")]
+  [(set_attr "type" "neon_logic_reg<q>")]
     )

     (define_insn "aarch64_simd_vec_set<mode>"
@@ -492,7 +492,7 @@ 
           gcc_unreachable ();
          }
       }
-  [(set_attr "type" "neon_from_gp<q>, neon_ins<q>, neon_load1_1reg<q>")]
+  [(set_attr "type" "neon_lane_from_gp<q>, neon_ins<q>,
neon_load1_1reg<q>")]
     )

     (define_insn "aarch64_simd_lshr<mode>"
@@ -832,7 +832,7 @@ 
           gcc_unreachable ();
           }
       }
-  [(set_attr "type" "neon_from_gp, neon_ins_q")]
+  [(set_attr "type" "neon_lane_from_gp, neon_ins_q")]
     )

     (define_expand "vec_setv2di"
@@ -2421,7 +2421,7 @@ 
         operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL
(operands[2])));
         return "smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%2]";
       }
-  [(set_attr "type" "neon_to_gp<q>")]
+  [(set_attr "type" "neon_lane_to_gp<q>")]
     )

     (define_insn "*aarch64_get_lane_zero_extendsi<mode>"
@@ -2435,7 +2435,7 @@ 
         operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL
(operands[2])));
         return "umov\\t%w0, %1.<Vetype>[%2]";
       }
-  [(set_attr "type" "neon_to_gp<q>")]
+  [(set_attr "type" "neon_lane_to_gp<q>")]
     )

     ;; Lane extraction of a value, neither sign nor zero extension
@@ -2461,7 +2461,7 @@ 
             gcc_unreachable ();
           }
       }
-  [(set_attr "type" "neon_to_gp<q>, neon_dup<q>, neon_store1_one_lane<q>")]
+  [(set_attr "type" "neon_lane_to_gp<q>, neon_dup<q>,
neon_store1_one_lane<q>")]
     )

     ;; In this insn, operand 1 should be low, and operand 2 the high part
of the
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index a0ee362..ab5fd58 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -803,7 +803,7 @@ 
          }
     }
       [(set_attr "type" 
"mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
-                     neon_from_gp<q>,neon_from_gp<q>, neon_dup")
+                     neon_lane_to_gp<q>,neon_reg_from_gp<q>, neon_dup")
        (set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes")]
     )

@@ -928,7 +928,7 @@ 
        stp\\txzr, xzr, %0
        ldr\\t%q0, %1
        str\\t%q1, %0"
-  [(set_attr "type" "multiple,f_mcr,f_mrc,neon_logic_q, \
+  [(set_attr "type" "multiple,f_mcr,f_mrc,neon_logic_reg_q, \
                                load2,store2,store2,f_loadd,f_stored")
        (set_attr "length" "8,8,8,4,4,4,4,4,4")
        (set_attr "simd" "*,*,*,yes,*,*,*,*,*")
diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md
index 3a47578..cc9a52a 100644
--- a/gcc/config/aarch64/thunderx.md
+++ b/gcc/config/aarch64/thunderx.md
@@ -207,13 +207,13 @@ 
     ;; Thunder simd move instruction types - 2/3 cycles
     (define_insn_reservation "thunderx_neon_move" 2
       (and (eq_attr "tune" "thunderx")
-       (eq_attr "type" "neon_logic, neon_bsl, neon_fp_compare_s, \
+       (eq_attr "type" "neon_logic_reg, neon_bsl, neon_fp_compare_s, \
                           neon_fp_compare_d, neon_move"))
       "thunderx_pipe1 + thunderx_simd")

     (define_insn_reservation "thunderx_neon_move_q" 3
       (and (eq_attr "tune" "thunderx")
-       (eq_attr "type" "neon_logic_q, neon_bsl_q, neon_fp_compare_s_q, \
+       (eq_attr "type" "neon_logic_reg_q, neon_bsl_q,
neon_fp_compare_s_q, \
                           neon_fp_compare_d_q, neon_move_q"))
       "thunderx_pipe1 + thunderx_simd, thunderx_simd")

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 8f02743..a7f7afa 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -2035,8 +2035,8 @@ 
                                                gen_highpart_mode (SImode,
DImode, operands[2]));

       }"
-  [(set_attr "type" "neon_logic,neon_logic,multiple,multiple,\
-                     multiple,multiple,neon_logic,neon_logic")
+  [(set_attr "type" "neon_logic_reg,neon_logic_imm,multiple,multiple,\
+                     multiple,multiple,neon_logic_reg,neon_logic_imm")
        (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,
                          avoid_neon_for_64bits,avoid_neon_for_64bits")
        (set_attr "length" "*,*,8,8,8,8,*,*")
@@ -2854,8 +2854,8 @@ 
                                                gen_highpart_mode (SImode,
DImode, operands[2]));

       }"
-  [(set_attr "type" "neon_logic,neon_logic,multiple,multiple,multiple,\
-                     multiple,neon_logic,neon_logic")
+  [(set_attr "type"
"neon_logic_reg,neon_logic_imm,multiple,multiple,multiple,\
+                     multiple,neon_logic_reg,neon_logic_imm")
        (set_attr "length" "*,*,8,8,8,8,*,*")
        (set_attr "arch"
"neon_for_64bits,neon_for_64bits,*,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")]
     )
@@ -3027,7 +3027,7 @@ 

       }"
       [(set_attr "length" "*,8,8,8,8,*")
-   (set_attr "type"
"neon_logic,multiple,multiple,multiple,multiple,neon_logic")
+   (set_attr "type"
"neon_logic_reg,multiple,multiple,multiple,multiple,neon_logic_reg")
        (set_attr "arch" "neon_for_64bits,*,*,*,*,avoid_neon_for_64bits")]
     )

diff --git a/gcc/config/arm/cortex-a15-neon.md
b/gcc/config/arm/cortex-a15-neon.md
index bc09cd6..3cd9a21 100644
--- a/gcc/config/arm/cortex-a15-neon.md
+++ b/gcc/config/arm/cortex-a15-neon.md
@@ -49,8 +49,9 @@ 
                                neon_add_widen, neon_neg, neon_neg_q,\
                                neon_reduc_add, neon_reduc_add_q,\
                                neon_reduc_add_long, neon_sub, neon_sub_q,\
-                           neon_sub_long, neon_sub_widen, neon_logic,\
-                           neon_logic_q, neon_tst, neon_tst_q")
+                           neon_sub_long, neon_sub_widen, neon_logic_reg,\
+                           neon_logic_reg_q, neon_logic_imm,
neon_logic_imm_q,\
+                           neon_tst, neon_tst_q")
                 (const_string "neon_arith_basic")
               (eq_attr "type" "neon_abs, neon_abs_q,
neon_add_halve_narrow_q,\
                                neon_add_halve, neon_add_halve_q,\
@@ -152,15 +153,16 @@ 
               (eq_attr "type" "neon_bsl_q, neon_cls_q, neon_cnt_q,\
                                neon_rev_q, neon_permute_q")
                 (const_string "neon_bitops_q")
-          (eq_attr "type" "neon_from_gp")
+          (eq_attr "type" "neon_reg_from_gp, neon_lane_from_gp")
                 (const_string "neon_from_gp")
-          (eq_attr "type" "neon_from_gp_q")
+          (eq_attr "type" "neon_reg_from_gp_q, neon_lane_from_gp_q")
                 (const_string "neon_from_gp_q")
               (eq_attr "type" "neon_tbl3, neon_tbl4")
                 (const_string "neon_tbl3_tbl4")
               (eq_attr "type" "neon_zip_q")
                 (const_string "neon_zip_q")
-          (eq_attr "type" "neon_to_gp, neon_to_gp_q")
+          (eq_attr "type" "neon_reg_to_gp, neon_reg_to_gp_q,\
+                           neon_lane_to_gp, neon_lane_to_gp_q,")
                 (const_string "neon_to_gp")

               (eq_attr "type" "f_loads, f_loadd,\
diff --git a/gcc/config/arm/cortex-a17-neon.md
b/gcc/config/arm/cortex-a17-neon.md
index 95bc372..09d2516 100644
--- a/gcc/config/arm/cortex-a17-neon.md
+++ b/gcc/config/arm/cortex-a17-neon.md
@@ -48,8 +48,9 @@ 
                                neon_add_widen, neon_neg, neon_neg_q,\
                                neon_reduc_add, neon_reduc_add_q,\
                                neon_reduc_add_long, neon_sub, neon_sub_q,\
-                           neon_sub_long, neon_sub_widen, neon_logic,\
-                           neon_logic_q, neon_tst, neon_tst_q")
+                           neon_sub_long, neon_sub_widen, neon_logic_reg,\
+                           neon_logic_imm, neon_logic_reg_q,\
+                           neon_logic_imm_q, neon_tst, neon_tst_q")
                 (const_string "neon_arith_basic")
               (eq_attr "type" "neon_abs, neon_abs_q,
neon_add_halve_narrow_q,\
                                neon_add_halve, neon_add_halve_q,\
@@ -153,15 +154,16 @@ 
               (eq_attr "type" "neon_bsl_q, neon_cls_q, neon_cnt_q,\
                                neon_rev_q, neon_permute_q")
                 (const_string "neon_bitops_q")
-          (eq_attr "type" "neon_from_gp")
+          (eq_attr "type" "neon_reg_from_gp, neon_lane_from_gp")
                 (const_string "neon_from_gp")
-          (eq_attr "type" "neon_from_gp_q")
+          (eq_attr "type" "neon_reg_from_gp_q, neon_lane_from_gp_q")
                 (const_string "neon_from_gp_q")
               (eq_attr "type" "neon_tbl3, neon_tbl4")
                 (const_string "neon_tbl3_tbl4")
               (eq_attr "type" "neon_zip_q")
                 (const_string "neon_zip_q")
-          (eq_attr "type" "neon_to_gp, neon_to_gp_q")
+          (eq_attr "type" "neon_reg_to_gp, neon_lane_to_gp,
neon_reg_to_gp_q,
+                           neon_lane_to_gp_q")
                 (const_string "neon_to_gp")

               (eq_attr "type" "neon_load1_1reg, neon_load1_1reg_q,\
diff --git a/gcc/config/arm/cortex-a8-neon.md
b/gcc/config/arm/cortex-a8-neon.md
index 1bb0ab2..ea3c29f 100644
--- a/gcc/config/arm/cortex-a8-neon.md
+++ b/gcc/config/arm/cortex-a8-neon.md
@@ -42,7 +42,8 @@ 
 
neon_vld3_vld4_all_lanes,neon_mcr,neon_mcr_2_mcrr,neon_mrc,neon_mrrc,
        neon_ldm_2,neon_stm_2,none,unknown"
       (cond [
-          (eq_attr "type" "neon_logic, neon_logic_q,\
+          (eq_attr "type" "neon_logic_reg, neon_logic_reg_q,\
+                           neon_logic_imm, neon_logic_imm_q,\
                                neon_bsl, neon_cls, neon_cnt,\
                                neon_add, neon_add_q")
                               (const_string "neon_int_1")
@@ -224,13 +225,13 @@ 
               (eq_attr "type" "neon_store3_one_lane,
neon_store3_one_lane_q,\
                                neon_store4_one_lane,
neon_store4_one_lane_q")
                                (const_string "neon_vst3_vst4_lane")
-          (eq_attr "type" "neon_from_gp, f_mcr")
+          (eq_attr "type" "neon_reg_from_gp, neon_lane_from_gp, f_mcr")
                                (const_string "neon_mcr")
-          (eq_attr "type" "neon_from_gp_q, f_mcrr")
+          (eq_attr "type" "neon_reg_from_gp_q, neon_lane_from_gp_q,
f_mcrr")
                                (const_string "neon_mcr_2_mcrr")
-          (eq_attr "type" "neon_to_gp, f_mrc")
+          (eq_attr "type" "neon_reg_to_gp, neon_lane_to_gp, f_mrc")
                                (const_string "neon_mrc")
-          (eq_attr "type" "neon_to_gp_q, f_mrrc")
+          (eq_attr "type" "neon_reg_to_gp_q, neon_lane_to_gp_q, f_mrrc")
                                (const_string "neon_mrrc")]
               (const_string "unknown")))

diff --git a/gcc/config/arm/cortex-a9-neon.md
b/gcc/config/arm/cortex-a9-neon.md
index 3ff93f9..de1b5ec 100644
--- a/gcc/config/arm/cortex-a9-neon.md
+++ b/gcc/config/arm/cortex-a9-neon.md
@@ -43,7 +43,8 @@ 
 
neon_vld3_vld4_all_lanes,neon_mcr,neon_mcr_2_mcrr,neon_mrc,neon_mrrc,
        neon_ldm_2,neon_stm_2,none,unknown"
       (cond [
-          (eq_attr "type" "neon_logic, neon_logic_q,\
+          (eq_attr "type" "neon_logic_reg, neon_logic_reg_q,\
+                           neon_logic_imm, neon_logic_imm_q,\
                                neon_bsl, neon_cls, neon_cnt,\
                                neon_add, neon_add_q")
                               (const_string "neon_int_1")
@@ -224,13 +225,13 @@ 
               (eq_attr "type" "neon_store3_one_lane,
neon_store3_one_lane_q,\
                                neon_store4_one_lane,
neon_store4_one_lane_q")
                                (const_string "neon_vst3_vst4_lane")
-          (eq_attr "type" "neon_from_gp")
+          (eq_attr "type" "neon_reg_from_gp, neon_lane_from_gp")
                                (const_string "neon_mcr")
-          (eq_attr "type" "neon_from_gp_q")
+          (eq_attr "type" "neon_reg_from_gp_q, neon_lane_from_gp_q")
                                (const_string "neon_mcr_2_mcrr")
-          (eq_attr "type" "neon_to_gp")
+          (eq_attr "type" "neon_reg_to_gp, neon_lane_to_gp")
                                (const_string "neon_mrc")
-          (eq_attr "type" "neon_to_gp_q")
+          (eq_attr "type" "neon_reg_to_gp_q, neon_lane_to_gp_q")
                                (const_string "neon_mrrc")]
               (const_string "unknown")))

diff --git a/gcc/config/arm/marvell-whitney.md
b/gcc/config/arm/marvell-whitney.md
index 57391a7..9b24a68 100644
--- a/gcc/config/arm/marvell-whitney.md
+++ b/gcc/config/arm/marvell-whitney.md
@@ -170,7 +170,7 @@ 
                                (const_string "wTP41")
               (eq_attr "type" "neon_permute_q,neon_zip_q")
                                (const_string "wTP42")
-          (eq_attr "type" "neon_bsl,neon_logic")
+          (eq_attr "type" "neon_bsl,neon_logic_imm")
                                (const_string "wTP43")
               (eq_attr "type" "neon_arith_acc,neon_shift_acc")
                               (if_then_else (match_test
@@ -182,9 +182,9 @@ 
                               "marvell_whitney_vector_element_size_is_byte
(insn)")
                                             (const_string "wTP44")
                                             (const_string "wTP46"))
-          (eq_attr "type" "neon_logic_q")
+          (eq_attr "type" "neon_logic_imm_q")
                               (const_string "wTP44")
-          (eq_attr "type" "neon_cls,neon_cnt,neon_dup,neon_ext,\
+          (eq_attr "type"
"neon_cls,neon_cnt,neon_dup,neon_ext,neon_logic_reg,\

neon_fp_recpe_s,neon_fp_rsqrte_s,neon_minmax,\
                                neon_move,neon_reduc_minmax,neon_rev")
                               (const_string "wTP47")
@@ -192,7 +192,7 @@ 

neon_fp_recpe_s_q,neon_fp_rsqrte_s_q,neon_minmax_q,\

neon_move_q,neon_move_narrow_q,neon_reduc_minmax_q,\
                                neon_rev_q,neon_sat_shift_imm_narrow_q,\
-                           neon_shift_imm_narrow_q")
+                           neon_shift_imm_narrow_q,neon_logic_reg_q")
                                (const_string "wTP48")
               (eq_attr "type" "neon_abd_long,neon_abs,neon_neg,neon_qabs,\

neon_qneg,neon_sat_shift_imm,neon_shift_imm_long,\
@@ -229,15 +229,15 @@ 

neon_sat_mla_s_long,neon_sat_mla_h_scalar_long,\
                                neon_sat_mla_s_scalar_long")
                                (const_string "wTP54")
-          (eq_attr "type" "f_flag,f_mrc,f_mrrc")
+          (eq_attr "type"
"f_flag,f_mrc,f_mrrc,neon_reg_to_gp,neon_reg_to_gp_q")
                                (const_string "wTP57")
-          (eq_attr "type" "neon_to_gp,neon_to_gp_q")
+          (eq_attr "type" "neon_lane_to_gp,neon_lane_to_gp_q")
                                (const_string "wTP55")
-          (eq_attr "type" "f_mcr,f_mcrr")
+          (eq_attr "type" "f_mcr,f_mcrr,neon_reg_from_gp")
                                (const_string "wTP58")
-          (eq_attr "type" "neon_from_gp_q")
+          (eq_attr "type" "neon_reg_from_gp_q")
                                (const_string "wTP59")
-          (eq_attr "type" "neon_from_gp")
+          (eq_attr "type" "neon_lane_from_gp, neon_lane_from_gp_q")
                                (const_string "wTP56")]
               (const_string "unknown")))

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 22318de..009ce6c 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -61,7 +61,7 @@ 
         }
     }
      [(set_attr "type" "neon_move<q>,neon_store1_1reg,neon_move<q>,\
-                    neon_load1_1reg,
neon_to_gp<q>,neon_from_gp<q>,mov_reg,\
+                    neon_load1_1reg,
neon_reg_to_gp<q>,neon_reg_from_gp<q>,mov_reg,\
                         neon_load1_2reg, neon_store1_2reg")
       (set_attr "length" "4,4,4,4,4,4,8,8,8")
       (set_attr "arm_pool_range"     "*,*,*,1020,*,*,*,1020,*")
@@ -106,7 +106,7 @@ 
         }
     }
       [(set_attr "type" "neon_move_q,neon_store2_2reg_q,neon_move_q,\
-                     neon_load2_2reg_q,neon_to_gp_q,neon_from_gp_q,\
+
neon_load2_2reg_q,neon_reg_to_gp_q,neon_reg_from_gp_q,\
                          mov_reg,neon_load1_4reg,neon_store1_4reg")
        (set_attr "length" "4,8,4,8,8,8,16,8,16")
        (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")
@@ -317,7 +317,7 @@ 
       else
         return "vmov.<V_sz_elem>\t%P0[%c2], %1";
     }
-  [(set_attr "type" "neon_load1_all_lanes<q>,neon_from_gp<q>")])
+  [(set_attr "type" "neon_load1_all_lanes<q>,neon_lane_from_gp<q>")])

     (define_insn "vec_set<mode>_internal"
       [(set (match_operand:VQ 0 "s_register_operand" "=w,w")
@@ -345,7 +345,7 @@ 
       else
         return "vmov.<V_sz_elem>\t%P0[%c2], %1";
     }
-  [(set_attr "type" "neon_load1_all_lanes<q>,neon_from_gp<q>")]
+  [(set_attr "type" "neon_load1_all_lanes<q>,neon_lane_from_gp<q>")]
     )

     (define_insn "vec_setv2di_internal"
@@ -367,7 +367,7 @@ 
       else
         return "vmov\t%P0, %Q1, %R1";
     }
-  [(set_attr "type" "neon_load1_all_lanes_q,neon_from_gp_q")]
+  [(set_attr "type" "neon_load1_all_lanes_q,neon_reg_from_gp_q")]
     )

     (define_expand "vec_set<mode>"
@@ -401,7 +401,7 @@ 
       else
         return "vmov.<V_uf_sclr>\t%0, %P1[%c2]";
     }
-  [(set_attr "type" "neon_store1_one_lane<q>,neon_to_gp<q>")]
+  [(set_attr "type" "neon_store1_one_lane<q>,neon_lane_to_gp<q>")]
     )

     (define_insn "vec_extract<mode>"
@@ -427,7 +427,7 @@ 
       else
         return "vmov.<V_uf_sclr>\t%0, %P1[%c2]";
     }
-  [(set_attr "type" "neon_store1_one_lane<q>,neon_to_gp<q>")]
+  [(set_attr "type" "neon_store1_one_lane<q>,neon_lane_to_gp<q>")]
     )

     (define_insn "vec_extractv2di"
@@ -446,7 +446,7 @@ 
       else
         return "vmov\t%Q0, %R0, %P1  @ v2di";
     }
-  [(set_attr "type" "neon_store1_one_lane_q,neon_to_gp_q")]
+  [(set_attr "type" "neon_store1_one_lane_q,neon_reg_to_gp_q")]
     )

     (define_expand "vec_init<mode>"
@@ -654,7 +654,7 @@ 
         default: gcc_unreachable ();
         }
     }
-  [(set_attr "type" "neon_logic<q>")]
+  [(set_attr "type" "neon_logic_reg<q>, neon_logic_imm<q>")]
     )

     ;; The concrete forms of the Neon immediate-logic instructions are
vbic and
@@ -676,7 +676,7 @@ 
         default: gcc_unreachable ();
         }
     }
-  [(set_attr "type" "neon_logic<q>")]
+  [(set_attr "type" "neon_logic_reg<q>, neon_logic_imm<q>")]
     )

     (define_insn "orn<mode>3_neon"
@@ -685,7 +685,7 @@ 
                    (match_operand:VDQ 1 "s_register_operand" "w")))]
       "TARGET_NEON"
       "vorn\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
-  [(set_attr "type" "neon_logic<q>")]
+  [(set_attr "type" "neon_logic_reg<q>")]
     )

     ;; TODO: investigate whether we should disable
@@ -723,7 +723,7 @@ 
             DONE;
           }
       }"
-  [(set_attr "type" "neon_logic,multiple,multiple,multiple")
+  [(set_attr "type" "neon_logic_reg,multiple,multiple,multiple")
        (set_attr "length" "*,16,8,8")
        (set_attr "arch" "any,a,t2,t2")]
     )
@@ -734,7 +734,7 @@ 
                    (match_operand:VDQ 1 "s_register_operand" "w")))]
       "TARGET_NEON"
       "vbic\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
-  [(set_attr "type" "neon_logic<q>")]
+  [(set_attr "type" "neon_logic_reg<q>")]
     )

     ;; Compare to *anddi_notdi_di.
@@ -747,7 +747,7 @@ 
        vbic\t%P0, %P1, %P2
        #
        #"
-  [(set_attr "type" "neon_logic,multiple,multiple")
+  [(set_attr "type" "neon_logic_reg,multiple,multiple")
        (set_attr "length" "*,8,8")]
     )

@@ -757,7 +757,7 @@ 
                    (match_operand:VDQ 2 "s_register_operand" "w")))]
       "TARGET_NEON"
       "veor\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
-  [(set_attr "type" "neon_logic<q>")]
+  [(set_attr "type" "neon_logic_reg<q>")]
     )

     (define_insn "one_cmpl<mode>2"
@@ -998,7 +998,7 @@ 
       "@
        vld1.32\t{%P0[0]}, %A1
        vmov.32\t%P0[0], %1"
-  [(set_attr "type" "neon_load1_1reg,neon_from_gp")]
+  [(set_attr "type" "neon_load1_1reg,neon_lane_from_gp")]
     )

     (define_insn "ashldi3_neon_noclobber"
@@ -2640,7 +2640,7 @@ 
         }
       return "vmov.s<V_sz_elem>\t%0, %P1[%c2]";
     }
-  [(set_attr "type" "neon_to_gp")]
+  [(set_attr "type" "neon_lane_to_gp")]
     )

     (define_insn "neon_vget_lane<mode>_zext_internal"
@@ -2659,7 +2659,7 @@ 
         }
       return "vmov.u<V_sz_elem>\t%0, %P1[%c2]";
     }
-  [(set_attr "type" "neon_to_gp")]
+  [(set_attr "type" "neon_lane_to_gp")]
     )

     (define_insn "neon_vget_lane<mode>_sext_internal"
@@ -2686,7 +2686,7 @@ 

       return "";
     }
-  [(set_attr "type" "neon_to_gp_q")]
+  [(set_attr "type" "neon_lane_to_gp_q")]
     )

     (define_insn "neon_vget_lane<mode>_zext_internal"
@@ -2713,7 +2713,7 @@ 

       return "";
     }
-  [(set_attr "type" "neon_to_gp_q")]
+  [(set_attr "type" "neon_lane_to_gp_q")]
     )

     (define_expand "neon_vget_lane<mode>"
@@ -2861,7 +2861,7 @@ 
             (vec_duplicate:VX (match_operand:<V_elem> 1
"s_register_operand" "r")))]
       "TARGET_NEON"
       "vdup.<V_sz_elem>\t%<V_reg>0, %1"
-  [(set_attr "type" "neon_from_gp<q>")]
+  [(set_attr "type" "neon_lane_from_gp<q>")]
     )

     (define_insn "neon_vdup_n<mode>"
@@ -2871,7 +2871,7 @@ 
       "@
       vdup.<V_sz_elem>\t%<V_reg>0, %1
       vdup.<V_sz_elem>\t%<V_reg>0, %y1"
-  [(set_attr "type" "neon_from_gp<q>,neon_dup<q>")]
+  [(set_attr "type" "neon_lane_from_gp<q>,neon_dup<q>")]
     )

     (define_expand "neon_vdup_ndi"
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index c1151f5..91475ef 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -273,8 +273,10 @@ 
     ; neon_reduc_add_acc_q
     ; neon_reduc_minmax
     ; neon_reduc_minmax_q
-; neon_logic
-; neon_logic_q
+; neon_logic_reg
+; neon_logic_reg_q
+; neon_logic_imm
+; neon_logic_imm_q
     ; neon_tst
     ; neon_tst_q
     ; neon_shift_imm
@@ -370,10 +372,14 @@ 
     ; neon_sat_mla_s_long
     ; neon_sat_mla_h_scalar_long
     ; neon_sat_mla_s_scalar_long
-; neon_to_gp
-; neon_to_gp_q
-; neon_from_gp
-; neon_from_gp_q
+; neon_reg_to_gp
+; neon_reg_to_gp_q
+; neon_reg_from_gp
+; neon_reg_from_gp_q
+; neon_lane_to_gp
+; neon_lane_to_gp_q
+; neon_lane_from_gp
+; neon_lane_from_gp_q
     ; neon_ldr
     ; neon_load1_1reg
     ; neon_load1_1reg_q
@@ -774,8 +780,10 @@ 
       neon_reduc_add_acc_q,\
       neon_reduc_minmax,\
       neon_reduc_minmax_q,\
-  neon_logic,\
-  neon_logic_q,\
+  neon_logic_reg,\
+  neon_logic_reg_q,\
+  neon_logic_imm,\
+  neon_logic_imm_q,\
       neon_tst,\
       neon_tst_q,\
     \
@@ -881,10 +889,14 @@ 
       neon_sat_mla_h_scalar_long,\
       neon_sat_mla_s_scalar_long,\
     \
-  neon_to_gp,\
-  neon_to_gp_q,\
-  neon_from_gp,\
-  neon_from_gp_q,\
+  neon_reg_to_gp,\
+  neon_reg_to_gp_q,\
+  neon_reg_from_gp,\
+  neon_reg_from_gp_q,\
+  neon_lane_to_gp,\
+  neon_lane_to_gp_q,\
+  neon_lane_from_gp,\
+  neon_lane_from_gp_q,\
     \
       neon_ldr,\
       neon_load1_1reg,\
@@ -1095,7 +1107,8 @@ 
               neon_arith_acc, neon_arith_acc_q, neon_reduc_add,\
               neon_reduc_add_q, neon_reduc_add_long, neon_reduc_add_acc,\
               neon_reduc_add_acc_q, neon_reduc_minmax, 
neon_reduc_minmax_q,\
-          neon_logic, neon_logic_q, neon_tst, neon_tst_q,\
+          neon_logic_reg, neon_logic_reg_q, neon_logic_imm,
neon_logic_imm_q,\
+          neon_tst, neon_tst_q,\
               neon_shift_imm, neon_shift_imm_q, neon_shift_imm_narrow_q,\