From patchwork Mon Jan 4 19:19:14 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 42208 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 243FFB6EE9 for ; Wed, 6 Jan 2010 09:09:04 +1100 (EST) Received: from localhost ([127.0.0.1]:49621 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NSHaH-0002Hr-0d for incoming@patchwork.ozlabs.org; Tue, 05 Jan 2010 17:09:01 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NSFVV-0002uQ-Np for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:55:58 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NSFVT-0002rb-03 for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:55:55 -0500 Received: from [199.232.76.173] (port=43081 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NSFVR-0002rQ-Mq for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:55:53 -0500 Received: from mx20.gnu.org ([199.232.41.8]:36449) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NSFVP-0005Ep-7V for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:55:51 -0500 Received: from are.twiddle.net ([75.149.56.221]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NRwFJ-0000E0-Jb for qemu-devel@nongnu.org; Mon, 04 Jan 2010 18:21:58 -0500 Received: by are.twiddle.net (Postfix, from userid 5000) id B56D0E22; Mon, 4 Jan 2010 15:08:37 -0800 (PST) Message-Id: <292071c796105a489c3cfaab6aa52a9a89b6c5f0.1262645165.git.rth@twiddle.net> In-Reply-To: References: From: Richard Henderson Date: Mon, 4 Jan 2010 11:19:14 -0800 To: qemu-devel@nongnu.org X-detected-operating-system: by mx20.gnu.org: GNU/Linux 2.6 (newer, 2) X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) Cc: laurent.desnogues@gmail.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 3/6] target-alpha: Reduce internal processor registers for user-mode. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The existing set of IPRs is totally irrelevant to user-mode emulation. Indeed, they most are irrelevant to implementing kernel-mode emulation, and would only be relevant to PAL-mode emulation, which I suspect that no one will ever attempt. Reducing the set of processor registers reduces the size of the CPU state. Signed-off-by: Richard Henderson --- linux-user/main.c | 4 +--- target-alpha/cpu.h | 6 ++++++ target-alpha/translate.c | 45 +++++++++++++++++++++++++++------------------ 3 files changed, 34 insertions(+), 21 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index a0d8ce7..91e5009 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3050,10 +3050,8 @@ int main(int argc, char **argv, char **envp) for(i = 0; i < 28; i++) { env->ir[i] = ((abi_ulong *)regs)[i]; } - env->ipr[IPR_USP] = regs->usp; - env->ir[30] = regs->usp; + env->ir[IR_SP] = regs->usp; env->pc = regs->pc; - env->unique = regs->unique; } #elif defined(TARGET_CRIS) { diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 4722415..3728d83 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -193,6 +193,11 @@ enum { /* Internal processor registers */ /* XXX: TOFIX: most of those registers are implementation dependant */ enum { +#if defined(CONFIG_USER_ONLY) + IPR_EXC_ADDR, + IPR_EXC_SUM, + IPR_EXC_MASK, +#else /* Ebox IPRs */ IPR_CC = 0xC0, /* 21264 */ IPR_CC_CTL = 0xC1, /* 21264 */ @@ -306,6 +311,7 @@ enum { IPR_VPTB, IPR_WHAMI, IPR_ALT_MODE, +#endif IPR_LAST, }; diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 87813e7..515c8c7 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -2721,7 +2721,6 @@ static const struct cpu_def_t cpu_defs[] = { CPUAlphaState * cpu_alpha_init (const char *cpu_model) { CPUAlphaState *env; - uint64_t hwpcb; int implver, amask, i, max; env = qemu_mallocz(sizeof(CPUAlphaState)); @@ -2752,24 +2751,34 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model) | FPCR_UNFD | FPCR_INED | FPCR_DNOD)); #endif pal_init(env); + /* Initialize IPR */ - hwpcb = env->ipr[IPR_PCBB]; - env->ipr[IPR_ASN] = 0; - env->ipr[IPR_ASTEN] = 0; - env->ipr[IPR_ASTSR] = 0; - env->ipr[IPR_DATFX] = 0; - /* XXX: fix this */ - // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8); - // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0); - // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16); - // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24); - env->ipr[IPR_FEN] = 0; - env->ipr[IPR_IPL] = 31; - env->ipr[IPR_MCES] = 0; - env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ - // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32); - env->ipr[IPR_SISR] = 0; - env->ipr[IPR_VIRBND] = -1ULL; +#if defined (CONFIG_USER_ONLY) + env->ipr[IPR_EXC_ADDR] = 0; + env->ipr[IPR_EXC_SUM] = 0; + env->ipr[IPR_EXC_MASK] = 0; +#else + { + uint64_t hwpcb; + hwpcb = env->ipr[IPR_PCBB]; + env->ipr[IPR_ASN] = 0; + env->ipr[IPR_ASTEN] = 0; + env->ipr[IPR_ASTSR] = 0; + env->ipr[IPR_DATFX] = 0; + /* XXX: fix this */ + // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8); + // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0); + // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16); + // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24); + env->ipr[IPR_FEN] = 0; + env->ipr[IPR_IPL] = 31; + env->ipr[IPR_MCES] = 0; + env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ + // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32); + env->ipr[IPR_SISR] = 0; + env->ipr[IPR_VIRBND] = -1ULL; + } +#endif qemu_init_vcpu(env); return env;