| Message ID | 1418761900-14035-8-git-send-email-hdegoede@redhat.com |
|---|---|
| State | Superseded |
| Delegated to: | Ian Campbell |
| Headers | show |
On Tue, 2014-12-16 at 21:31 +0100, Hans de Goede wrote: > The sun8i dram code sometimes wants to enable sigma delta mode, > add a parameter to allow this. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
On Tue, 16 Dec 2014 21:31:33 +0100 Hans de Goede <hdegoede@redhat.com> wrote: > The sun8i dram code sometimes wants to enable sigma delta mode, > add a parameter to allow this. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > --- > arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 9 +++++++-- > arch/arm/cpu/armv7/sunxi/dram_sun6i.c | 2 +- > arch/arm/include/asm/arch-sunxi/clock.h | 1 - > arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +++++ > 4 files changed, 13 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c > index 8e949c6..193e314 100644 > --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c > +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c > @@ -144,15 +144,20 @@ void clock_set_pll3(unsigned int clk) > &ccm->pll3_cfg); > } > > -void clock_set_pll5(unsigned int clk) > +void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) > { > struct sunxi_ccm_reg * const ccm = > (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; > const int k = 2; > const int m = 1; > > + if (sigma_delta_enable) > + writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); > + > /* PLL5 rate = 24000000 * n * k / m */ > - writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD | > + writel(CCM_PLL5_CTRL_EN | > + (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) | > + CCM_PLL5_CTRL_UPD | > CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | > CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); > > diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c > index 61bb8d4..bc6428a 100644 > --- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c > +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c > @@ -46,7 +46,7 @@ static void mctl_sys_init(void) > (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; > const int dram_clk_div = 2; > > - clock_set_pll5(DRAM_CLK * dram_clk_div); > + clock_set_pll5(DRAM_CLK * dram_clk_div, false); Would it make the code a bit more readable to have a named constant here (with SIGMA_DELTA as part of its name) instead of just true/false? The "foobar(true, true, false, true)" style is not exactly informative. I'm not insisting on this though. > clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, > CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST | > diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h > index 64acff3..505c363 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock.h > +++ b/arch/arm/include/asm/arch-sunxi/clock.h > @@ -26,7 +26,6 @@ int clock_init(void); > int clock_twi_onoff(int port, int state); > void clock_set_pll1(unsigned int hz); > void clock_set_pll3(unsigned int hz); > -void clock_set_pll5(unsigned int hz); > unsigned int clock_get_pll5p(void); > unsigned int clock_get_pll6(void); > void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz); > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > index 3d4fcd1..f807af3 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > @@ -185,6 +185,7 @@ struct sunxi_ccm_reg { > #define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4) > #define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) > #define CCM_PLL5_CTRL_UPD (0x1 << 20) > +#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24) > #define CCM_PLL5_CTRL_EN (0x1 << 31) > > #define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */ > @@ -274,6 +275,8 @@ struct sunxi_ccm_reg { > > #define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ > > +#define CCM_PLL5_PATTERN 0xd1303333 > + > /* ahb_reset0 offsets */ > #define AHB_RESET_OFFSET_GMAC 17 > #define AHB_RESET_OFFSET_MCTL 14 > @@ -308,4 +311,6 @@ struct sunxi_ccm_reg { > #define CCM_DE_CTRL_PLL10 (5 << 24) > #define CCM_DE_CTRL_GATE (1 << 31) > > +void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); > + > #endif /* _SUNXI_CLOCK_SUN6I_H */
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 8e949c6..193e314 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -144,15 +144,20 @@ void clock_set_pll3(unsigned int clk) &ccm->pll3_cfg); } -void clock_set_pll5(unsigned int clk) +void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) { struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; const int k = 2; const int m = 1; + if (sigma_delta_enable) + writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); + /* PLL5 rate = 24000000 * n * k / m */ - writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD | + writel(CCM_PLL5_CTRL_EN | + (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) | + CCM_PLL5_CTRL_UPD | CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c index 61bb8d4..bc6428a 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c @@ -46,7 +46,7 @@ static void mctl_sys_init(void) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; const int dram_clk_div = 2; - clock_set_pll5(DRAM_CLK * dram_clk_div); + clock_set_pll5(DRAM_CLK * dram_clk_div, false); clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST | diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 64acff3..505c363 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -26,7 +26,6 @@ int clock_init(void); int clock_twi_onoff(int port, int state); void clock_set_pll1(unsigned int hz); void clock_set_pll3(unsigned int hz); -void clock_set_pll5(unsigned int hz); unsigned int clock_get_pll5p(void); unsigned int clock_get_pll6(void); void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 3d4fcd1..f807af3 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -185,6 +185,7 @@ struct sunxi_ccm_reg { #define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4) #define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) #define CCM_PLL5_CTRL_UPD (0x1 << 20) +#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24) #define CCM_PLL5_CTRL_EN (0x1 << 31) #define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */ @@ -274,6 +275,8 @@ struct sunxi_ccm_reg { #define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ +#define CCM_PLL5_PATTERN 0xd1303333 + /* ahb_reset0 offsets */ #define AHB_RESET_OFFSET_GMAC 17 #define AHB_RESET_OFFSET_MCTL 14 @@ -308,4 +311,6 @@ struct sunxi_ccm_reg { #define CCM_DE_CTRL_PLL10 (5 << 24) #define CCM_DE_CTRL_GATE (1 << 31) +void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); + #endif /* _SUNXI_CLOCK_SUN6I_H */
The sun8i dram code sometimes wants to enable sigma delta mode, add a parameter to allow this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 9 +++++++-- arch/arm/cpu/armv7/sunxi/dram_sun6i.c | 2 +- arch/arm/include/asm/arch-sunxi/clock.h | 1 - arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +++++ 4 files changed, 13 insertions(+), 4 deletions(-)