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[PULL,26/30] target-mips: Fix DisasContext's ulri member initialization

Message ID 1418759356-14242-27-git-send-email-leon.alrae@imgtec.com
State New
Headers show

Commit Message

Leon Alrae Dec. 16, 2014, 7:49 p.m. UTC 
From: "Maciej W. Rozycki" <macro@codesourcery.com>

Set DisasContext's ulri member to 0 or 1 as with other bool members.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 571b7d7..f65ed84 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19116,7 +19116,7 @@  gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
     ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
     /* Restore delay slot state from the tb context.  */
     ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
-    ctx.ulri = env->CP0_Config3 & (1 << CP0C3_ULRI);
+    ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
     restore_cpu_state(env, &ctx);
 #ifdef CONFIG_USER_ONLY
         ctx.mem_idx = MIPS_HFLAG_UM;