diff mbox

target-mips: add CPU definition for MIPS-II

Message ID E484D272A3A61B4880CDF2E712E9279F4588121D@hhmail02.hh.imgtec.org
State New
Headers show

Commit Message

Daniel Sanders Dec. 15, 2014, 2:03 p.m. UTC 
Hi,

FWIW, the R6000 was a MIPS-II processor but I understand there was never a proper manual for it. http://www.linux-mips.org/wiki/R6000 has a small amount of information but not enough to accurately fill in qemu's structure.

> If this is really problematic for qemu, why don't we add an
> --enable-experimental-targets, --enable-generic-targets or something
> similar for generic/old CPU definitions?

One other possibility is to use a real CPU name such as R6000 but use reasonable guesses where information is unavailable. Is that a good compromise?

Daniel Sanders
Leading Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
www.imgtec.com<http://www.imgtec.com/>

From: Vasileios Kalintiris
Sent: 15 December 2014 10:09
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; Leon Alrae; Daniel Sanders
Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II

Hello Petar,

I've seen some older threads in the mailing list and I'm aware that
adding generic CPU definitions is something that should be avoided.
However, I don't have any real MIPS-II machine readily available at
the moment.

We need support for the MIPS-II ISA because we enabled the MIPS-II
target in the Clang/LLVM projects and we are running the LLVM
test-suite under QEMU. This allows us to verify that we are not
emitting invalid instructions or instructions that belong to another
version of the ISA. Also, Debian targets MIPS-II for compatibility
reasons and testing the code generation of the compiler for that ISA
is rather important.

So there's an actual need for a MIPS-II definition and it wouldn't
be convenient to have to maintain out-of-tree support for MIPS-II

If this is really problematic for qemu, why don't we add an
--enable-experimental-targets, --enable-generic-targets or something
similar for generic/old CPU definitions?

Thanks,
Vasileios Kalintiris

Comments

Leon Alrae Dec. 16, 2014, 11:59 a.m. UTC | #1 
Hi Daniel,

On 15/12/2014 14:03, Daniel Sanders wrote:
> Hi,
> 
>  
> 
> FWIW, the R6000 was a MIPS-II processor but I understand there was never
> a proper manual for it. http://www.linux-mips.org/wiki/R6000 has a small
> amount of information but not enough to accurately fill in qemu's structure.
> 
>  
> 
>> If this is really problematic for qemu, why don't we add an
>> --enable-experimental-targets, --enable-generic-targets or something
>> similar for generic/old CPU definitions?
> 
>  
> 
> One other possibility is to use a real CPU name such as R6000 but use
> reasonable guesses where information is unavailable. Is that a good
> compromise?

Adding R6000 sounds like the right way to go. Probably it won't be
accurately defined in QEMU until we can use the real hardware as a
reference, but this is still better than "MIPS-II generic CPU".

Thanks,
Leon
diff mbox

Patch

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 148b394..d4b1cd8 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -108,6 +108,29 @@  struct mips_def_t {
static const mips_def_t mips_defs[] =
{
     {
+        /* A generic CPU providing MIPS-II features.
+           FIXME: Eventually this should be replaced by a real CPU model. */
+        .name = "mips2-generic",
+        .CP0_PRid = 0x00018000,
+        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+                      (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                      (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+                      (0 << CP0C1_CA),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x30000011,
+        .CP1_fcr0 = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S),
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS2,
+        .mmu_type = MMU_TYPE_R4000,
+    },
+    {
         .name = "4Kc",
         .CP0_PRid = 0x00018000,
         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),