[U-Boot,19/26] mpc8260: remove PM825, PM826, PM828 board support

Message ID	1418653608-14177-20-git-send-email-yamada.m@jp.panasonic.com
State	Accepted
Delegated to:	Tom Rini
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Masahiro Yamada <yamada.m@jp.panasonic.com> To: u-boot@lists.denx.de Date: Mon, 15 Dec 2014 23:26:24 +0900 Message-Id: <1418653608-14177-20-git-send-email-yamada.m@jp.panasonic.com> In-Reply-To: <1418653608-14177-1-git-send-email-yamada.m@jp.panasonic.com> References: <1418653608-14177-1-git-send-email-yamada.m@jp.panasonic.com> Cc: Marek Vasut <marex@denx.de> Subject: [U-Boot] [PATCH 19/26] mpc8260: remove PM825, PM826, PM828 board support Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de

diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig index d9dba83..cb81cdc 100644 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -28,12 +28,6 @@ config TARGET_IPHASE4539 config TARGET_MUAS3001 bool "Support muas3001" -config TARGET_PM826 - bool "Support PM826" - -config TARGET_PM828 - bool "Support PM828" - config TARGET_KM82XX bool "Support km82xx" @@ -47,7 +41,5 @@ source "board/gw8260/Kconfig" source "board/iphase4539/Kconfig" source "board/keymile/km82xx/Kconfig" source "board/muas3001/Kconfig" -source "board/pm826/Kconfig" -source "board/pm828/Kconfig" endmenu diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c index 079b6e6..56f290c 100644 --- a/arch/powerpc/cpu/mpc8260/pci.c +++ b/arch/powerpc/cpu/mpc8260/pci.c @@ -22,10 +22,6 @@ #include <fdt_support.h> #endif -#if defined CONFIG_PM826 -DECLARE_GLOBAL_DATA_PTR; -#endif - /* * Local->PCI map (from CPU) controlled by * MPC826x master window @@ -342,17 +338,10 @@ void pci_mpc8250_init (struct pci_controller *hose) hose->last_busno = 0xff; /* System memory space */ -#if defined CONFIG_PM826 - pci_set_region (hose->regions + 0, - PCI_SLV_MEM_BUS, - PCI_SLV_MEM_LOCAL, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); -#else pci_set_region (hose->regions + 0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE, 0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); -#endif /* PCI memory space */ pci_set_region (hose->regions + 1, diff --git a/board/pm826/Kconfig b/board/pm826/Kconfig deleted file mode 100644 index dd11b7a..0000000 --- a/board/pm826/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_PM826 - -config SYS_BOARD - default "pm826" - -config SYS_CONFIG_NAME - default "PM826" - -endif diff --git a/board/pm826/MAINTAINERS b/board/pm826/MAINTAINERS deleted file mode 100644 index 41df4c9..0000000 --- a/board/pm826/MAINTAINERS +++ /dev/null @@ -1,13 +0,0 @@ -PM826 BOARD -M: Wolfgang Denk <wd@denx.de> -S: Maintained -F: board/pm826/ -F: include/configs/PM826.h -F: configs/PM825_defconfig -F: configs/PM825_BIGFLASH_defconfig -F: configs/PM825_ROMBOOT_defconfig -F: configs/PM825_ROMBOOT_BIGFLASH_defconfig -F: configs/PM826_defconfig -F: configs/PM826_BIGFLASH_defconfig -F: configs/PM826_ROMBOOT_defconfig -F: configs/PM826_ROMBOOT_BIGFLASH_defconfig diff --git a/board/pm826/Makefile b/board/pm826/Makefile deleted file mode 100644 index c515f81..0000000 --- a/board/pm826/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = pm826.o flash.o diff --git a/board/pm826/flash.c b/board/pm826/flash.c deleted file mode 100644 index 786a29b..0000000 --- a/board/pm826/flash.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for Intel devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (volatile unsigned long *baseaddr, - flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - info->sector_count = info->size = 0; - info->flash_id = FLASH_UNKNOWN; - - /* Write query command sequence and test FLASH answer - */ - baseaddr[0] = 0x00980098; - baseaddr[1] = 0x00980098; - - flashtest_h = baseaddr[0]; /* manufacturer ID */ - flashtest_l = baseaddr[1]; - - if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) - return (0); /* no or unknown flash */ - - flashtest_h = baseaddr[2]; /* device ID */ - flashtest_l = baseaddr[3]; - - if (flashtest_h != flashtest_l) - return (0); - - switch (flashtest_h) { - case INTEL_ID_28F160C3B: - info->flash_id = FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F160F3B: - info->flash_id = FLASH_28F160F3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F640C3B: - info->flash_id = FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ - break; - default: - return (0); /* no or unknown flash */ - } - - info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ - - if (info->flash_id & FLASH_BTYPE) { - volatile unsigned long *tmp = baseaddr; - - /* set up sector start adress table (bottom sector type) - * AND unlock the sectors (if our chip is 160C3 or 640C3) - */ - for (i = 0; i < info->sector_count; i++) { - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { - tmp[0] = 0x00600060; - tmp[1] = 0x00600060; - tmp[0] = 0x00D000D0; - tmp[1] = 0x00D000D0; - } - info->start[i] = (uint) tmp; - tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ - } - } - - memset (info->protect, 0, info->sector_count); - - baseaddr[0] = 0x00FF00FF; - baseaddr[1] = 0x00FF00FF; - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known - */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* protect monitor and environment sectors - */ - -#ifndef CONFIG_BOOT_ROM - /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE - * but we shouldn't protect it. - */ - -# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] - ); -# endif -#endif /* CONFIG_BOOT_ROM */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x89: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf ("28F160C3B (16 M, bottom sector)\n"); - break; - case FLASH_28F160F3B: - printf ("28F160F3B (16 M, bottom sector)\n"); - break; - case FLASH_28F640C3B: - printf ("28F640C3B (64 M, bottom sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors - */ - for (sect = s_first; sect <= s_last; sect++) { - volatile ulong *addr = - (volatile unsigned long *) info->start[sect]; - - start = get_timer (0); - last = start; - if (info->protect[sect] == 0) { - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - /* Erase the block - */ - addr[0] = 0x00200020; - addr[1] = 0x00200020; - addr[0] = 0x00D000D0; - addr[1] = 0x00D000D0; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - last = start; - while ((addr[0] & 0x00800080) != 0x00800080 || - (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (erase suspended!)\n"); - /* Suspend erase - */ - addr[0] = 0x00B000B0; - addr[1] = 0x00B000B0; - goto DONE; - } - /* show that we're waiting - */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { - printf ("*** ERROR: erase failed!\n"); - goto DONE; - } - } - /* Clear status register and reset to read mode - */ - addr[0] = 0x00500050; - addr[1] = 0x00500050; - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - - printf (" done\n"); - -DONE: - return 0; -} - -static int write_word (flash_info_t *, volatile unsigned long *, ulong); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong v; - int i, l, cc = cnt, res = 0; - - - for (v=0; cc > 0; addr += 4, cc -= 4 - l) { - l = (addr & 3); - addr &= ~3; - - for (i = 0; i < 4; i++) { - v = (v << 8) + (i < l || i - l >= cc ? - *((unsigned char *) addr + i) : *src++); - } - - if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) - break; - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, volatile unsigned long *addr, - ulong data) -{ - int flag, res = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - *addr = 0x00400040; - *addr = data; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - /* Suspend program - */ - *addr = 0x00B000B0; - res = 1; - goto OUT; - } - } - - if (*addr & 0x00220022) { - printf ("*** ERROR: program failed!\n"); - res = 1; - } - -OUT: - /* Clear status register and reset to read mode - */ - *addr = 0x00500050; - *addr = 0x00FF00FF; - - return (res); -} diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c deleted file mode 100644 index 93bb1b4..0000000 --- a/board/pm826/pm826.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> -#include <pci.h> -#include <netdev.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */ -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) -#ifdef CONFIG_ETHER_ON_FCC2 -#error "SCC1 conflicts with FCC2" -#endif - /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ -#else - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */ -#endif - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */ - /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */ - /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */ - /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - puts ("Board: PM826\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - - *orx_ptr = orx | ~(size - 1); - - return (size); -} - - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - ulong size8, size9; -#endif - ulong psize = 32 * 1024 * 1024; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:8COL) "); - } -#endif - return (psize); -} - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/pm828/Kconfig b/board/pm828/Kconfig deleted file mode 100644 index e7970a3..0000000 --- a/board/pm828/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_PM828 - -config SYS_BOARD - default "pm828" - -config SYS_CONFIG_NAME - default "PM828" - -endif diff --git a/board/pm828/MAINTAINERS b/board/pm828/MAINTAINERS deleted file mode 100644 index 97c1ccc..0000000 --- a/board/pm828/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -PM828 BOARD -#M: - -S: Maintained -F: board/pm828/ -F: include/configs/PM828.h -F: configs/PM828_defconfig -F: configs/PM828_PCI_defconfig -F: configs/PM828_ROMBOOT_defconfig -F: configs/PM828_ROMBOOT_PCI_defconfig diff --git a/board/pm828/Makefile b/board/pm828/Makefile deleted file mode 100644 index 0afffb7..0000000 --- a/board/pm828/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = pm828.o flash.o diff --git a/board/pm828/flash.c b/board/pm828/flash.c deleted file mode 100644 index 8888560..0000000 --- a/board/pm828/flash.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for Intel devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (volatile unsigned long *baseaddr, - flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - info->sector_count = info->size = 0; - info->flash_id = FLASH_UNKNOWN; - - /* Write query command sequence and test FLASH answer - */ - baseaddr[0] = 0x00980098; - baseaddr[1] = 0x00980098; - - flashtest_h = baseaddr[0]; /* manufacturer ID */ - flashtest_l = baseaddr[1]; - - if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) - return (0); /* no or unknown flash */ - - flashtest_h = baseaddr[2]; /* device ID */ - flashtest_l = baseaddr[3]; - - if (flashtest_h != flashtest_l) - return (0); - - switch (flashtest_h) { - case INTEL_ID_28F160C3B: - info->flash_id = FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F160F3B: - info->flash_id = FLASH_28F160F3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F640C3B: - info->flash_id = FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ - break; - default: - return (0); /* no or unknown flash */ - } - - info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ - - if (info->flash_id & FLASH_BTYPE) { - volatile unsigned long *tmp = baseaddr; - - /* set up sector start adress table (bottom sector type) - * AND unlock the sectors (if our chip is 160C3 or 640c3) - */ - for (i = 0; i < info->sector_count; i++) { - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { - tmp[0] = 0x00600060; - tmp[1] = 0x00600060; - tmp[0] = 0x00D000D0; - tmp[1] = 0x00D000D0; - } - info->start[i] = (uint) tmp; - tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ - } - } - - memset (info->protect, 0, info->sector_count); - - baseaddr[0] = 0x00FF00FF; - baseaddr[1] = 0x00FF00FF; - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known - */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* protect monitor and environment sectors - */ - -#ifndef CONFIG_BOOT_ROM - /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE - * but we shouldn't protect it. - */ - -# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] - ); -# endif -#endif /* CONFIG_BOOT_ROM */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x89: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf ("28F160C3B (16 M, bottom sector)\n"); - break; - case FLASH_28F160F3B: - printf ("28F160F3B (16 M, bottom sector)\n"); - break; - case FLASH_28F640C3B: - printf ("28F640C3B (64 M, bottom sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors - */ - for (sect = s_first; sect <= s_last; sect++) { - volatile ulong *addr = - (volatile unsigned long *) info->start[sect]; - - start = get_timer (0); - last = start; - if (info->protect[sect] == 0) { - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - /* Erase the block - */ - addr[0] = 0x00200020; - addr[1] = 0x00200020; - addr[0] = 0x00D000D0; - addr[1] = 0x00D000D0; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - last = start; - while ((addr[0] & 0x00800080) != 0x00800080 || - (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (erase suspended!)\n"); - /* Suspend erase - */ - addr[0] = 0x00B000B0; - addr[1] = 0x00B000B0; - goto DONE; - } - /* show that we're waiting - */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { - printf ("*** ERROR: erase failed!\n"); - goto DONE; - } - } - /* Clear status register and reset to read mode - */ - addr[0] = 0x00500050; - addr[1] = 0x00500050; - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - - printf (" done\n"); - -DONE: - return 0; -} - -static int write_word (flash_info_t *, volatile unsigned long *, ulong); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong v; - int i, l, cc = cnt, res = 0; - - - for (v=0; cc > 0; addr += 4, cc -= 4 - l) { - l = (addr & 3); - addr &= ~3; - - for (i = 0; i < 4; i++) { - v = (v << 8) + (i < l || i - l >= cc ? - *((unsigned char *) addr + i) : *src++); - } - - if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) - break; - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, volatile unsigned long *addr, - ulong data) -{ - int flag, res = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - *addr = 0x00400040; - *addr = data; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - /* Suspend program - */ - *addr = 0x00B000B0; - res = 1; - goto OUT; - } - } - - if (*addr & 0x00220022) { - printf ("*** ERROR: program failed!\n"); - res = 1; - } - -OUT: - /* Clear status register and reset to read mode - */ - *addr = 0x00500050; - *addr = 0x00FF00FF; - - return (res); -} diff --git a/board/pm828/pm828.c b/board/pm828/pm828.c deleted file mode 100644 index f446543..0000000 --- a/board/pm828/pm828.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> -#include <pci.h> -#include <netdev.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */ -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) -#ifdef CONFIG_ETHER_ON_FCC2 -#error "SCC1 conflicts with FCC2" -#endif - /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ -#else - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */ -#endif - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */ - /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */ - /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */ - /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - puts ("Board: PM828\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile ulong cnt, val; - volatile ulong *addr; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - int i; - ulong save[32]; /* to make test non-destructive */ - ulong maxsize; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - /* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - i = 0; - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = (volatile ulong *) base + cnt; /* pointer arith! */ - save[i++] = *addr; - *addr = ~cnt; - } - - addr = (volatile ulong *) base; - save[i] = *addr; - *addr = 0; - - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *) base + cnt; /* pointer arith! */ - val = *addr; - *addr = save[--i]; - if (val != ~cnt) { - /* Write the actual size to ORx - */ - *orx_ptr = orx | ~(cnt * sizeof (long) - 1); - return (cnt * sizeof (long)); - } - } - return (maxsize); -} - - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - ulong size8, size9; -#endif - ulong psize = 32 * 1024 * 1024; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:8COL) "); - } -#endif - return (psize); -} - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/configs/PM825_BIGFLASH_defconfig b/configs/PM825_BIGFLASH_defconfig deleted file mode 100644 index 75efcdd..0000000 --- a/configs/PM825_BIGFLASH_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM826=y diff --git a/configs/PM825_ROMBOOT_BIGFLASH_defconfig b/configs/PM825_ROMBOOT_BIGFLASH_defconfig deleted file mode 100644 index 28ff17f..0000000 --- a/configs/PM825_ROMBOOT_BIGFLASH_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM826=y diff --git a/configs/PM825_ROMBOOT_defconfig b/configs/PM825_ROMBOOT_defconfig deleted file mode 100644 index f5233fa..0000000 --- a/configs/PM825_ROMBOOT_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM826=y diff --git a/configs/PM825_defconfig b/configs/PM825_defconfig deleted file mode 100644 index 459cdba..0000000 --- a/configs/PM825_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,SYS_TEXT_BASE=0xFF000000" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM826=y diff --git a/configs/PM826_BIGFLASH_defconfig b/configs/PM826_BIGFLASH_defconfig deleted file mode 100644 index 0acf9d2..0000000 --- a/configs/PM826_BIGFLASH_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="FLASH_32MB,SYS_TEXT_BASE=0x40000000" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM826=y diff --git a/configs/PM826_ROMBOOT_BIGFLASH_defconfig b/configs/PM826_ROMBOOT_BIGFLASH_defconfig deleted file mode 100644 index af8d4c9..0000000 --- a/configs/PM826_ROMBOOT_BIGFLASH_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM826=y diff --git a/configs/PM826_ROMBOOT_defconfig b/configs/PM826_ROMBOOT_defconfig deleted file mode 100644 index 7d3e1c3..0000000 --- a/configs/PM826_ROMBOOT_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM,SYS_TEXT_BASE=0xFF800000" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM826=y diff --git a/configs/PM826_defconfig b/configs/PM826_defconfig deleted file mode 100644 index b2f9d34..0000000 --- a/configs/PM826_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM826=y diff --git a/configs/PM828_PCI_defconfig b/configs/PM828_PCI_defconfig deleted file mode 100644 index 9b68562..0000000 --- a/configs/PM828_PCI_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM828=y diff --git a/configs/PM828_ROMBOOT_PCI_defconfig b/configs/PM828_ROMBOOT_PCI_defconfig deleted file mode 100644 index 8120058..0000000 --- a/configs/PM828_ROMBOOT_PCI_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM828=y diff --git a/configs/PM828_ROMBOOT_defconfig b/configs/PM828_ROMBOOT_defconfig deleted file mode 100644 index 7c8980e..0000000 --- a/configs/PM828_ROMBOOT_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM,SYS_TEXT_BASE=0xFF800000" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM828=y diff --git a/configs/PM828_defconfig b/configs/PM828_defconfig deleted file mode 100644 index 15887ca..0000000 --- a/configs/PM828_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_PM828=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index d358d62..f1c2f8b 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,9 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +PM825 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de> +PM826 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de> +PM828 powerpc mpc8260 - - MPC8266ADS powerpc mpc8260 - - Rune Torgersen <runet@innovsys.com> VoVPN-GW powerpc mpc8260 - - ep8260 powerpc mpc8260 - - Frank Panno <fpanno@delphintech.com> diff --git a/include/configs/PM826.h b/include/configs/PM826.h deleted file mode 100644 index 6416ad5..0000000 --- a/include/configs/PM826.h +++ /dev/null @@ -1,534 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef CONFIG_SYS_RAMBOOT - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_PM826 1 /* ...on a PM8260 module */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFF000000 /* Standard: boot 64-bit flash */ -#endif - -#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ - -/* - * select ethernet configuration - * - * if CONFIG_ETHER_ON_SCC is selected, then - * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) - * - * if CONFIG_ETHER_ON_FCC is selected, then - * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ - -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ - -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -/* - * - Rx-CLK is CLK11 - * - Tx-CLK is CLK10 - */ -#define CONFIG_ETHER_ON_FCC1 -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -#ifndef CONFIG_DB_CR826_J30x_ON -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) -#else -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) -#endif -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK14 - */ -#define CONFIG_ETHER_ON_FCC2 -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -/* - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 64000000 /* in Hz */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_CMD_PCI -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash and Boot ROM mapping - */ -#ifdef CONFIG_FLASH_32MB -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 0x02000000 -#else -#define CONFIG_SYS_FLASH0_BASE 0xFF000000 -#define CONFIG_SYS_FLASH0_SIZE 0x00800000 -#endif -#define CONFIG_SYS_BOOTROM_BASE 0xFF800000 -#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 -#define CONFIG_SYS_DOC_BASE 0xFF800000 -#define CONFIG_SYS_DOC_SIZE 0x00100000 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#ifdef CONFIG_FLASH_32MB -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ -#else -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#endif -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to EEPROM later */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) -#define CONFIG_ENV_SIZE 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -/* Final version: environment in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_ENV_OFFSET 512 -#define CONFIG_ENV_SIZE (2048 - 512) -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if defined(CONFIG_BOOT_ROM) -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ - -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR (SCCR_DFBRG00) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CONFIG_SYS_INIT_LOCAL_SDRAM - - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_MIN_AM_MASK 0xC0000000 - -/* - * we use the same values for 32 MB and 128 MB SDRAM - * refresh rate = 7.73 uS (64 MHz Bus Clock) - */ -#define CONFIG_SYS_MPTPR 0x2000 -#define CONFIG_SYS_PSRT 0x0E - -#define CONFIG_SYS_MRS_OFFS 0x00000000 - - -#if defined(CONFIG_BOOT_ROM) -/* - * Bank 0 - Boot ROM (8 bit wide) - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Flash (64 bit wide) - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#else /* ! CONFIG_BOOT_ROM */ - -/* - * Bank 0 - Flash (64 bit wide) - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Disk-On-Chip - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#endif /* CONFIG_BOOT_ROM */ - -/* Bank 2 - SDRAM - */ - -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL -#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/PM828.h b/include/configs/PM828.h deleted file mode 100644 index e17fbfb..0000000 --- a/include/configs/PM828.h +++ /dev/null @@ -1,528 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef CONFIG_SYS_RAMBOOT - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_PM828 1 /* ...on a PM828 module */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x40000000 /* Standard: boot 64-bit flash */ -#endif - -#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ - -/* - * select ethernet configuration - * - * if CONFIG_ETHER_ON_SCC is selected, then - * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) - * - * if CONFIG_ETHER_ON_FCC is selected, then - * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ - -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ - -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -/* - * - Rx-CLK is CLK11 - * - Tx-CLK is CLK10 - */ -#define CONFIG_ETHER_ON_FCC1 -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -#ifndef CONFIG_DB_CR826_J30x_ON -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) -#else -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) -#endif -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK14 - */ -#define CONFIG_ETHER_ON_FCC2 -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -/* - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_CMD_PCI -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash and Boot ROM mapping - */ - -#define CONFIG_SYS_BOOTROM_BASE 0xFF800000 -#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 0x02000000 -#define CONFIG_SYS_DOC_BASE 0xFF800000 -#define CONFIG_SYS_DOC_SIZE 0x00100000 - - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to EEPROM later */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) -#define CONFIG_ENV_SIZE 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -/* Final version: environment in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_ENV_OFFSET 512 -#define CONFIG_ENV_SIZE (2048 - 512) -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if defined(CONFIG_BOOT_ROM) -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ - -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR (SCCR_DFBRG00) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CONFIG_SYS_INIT_LOCAL_SDRAM - - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_MIN_AM_MASK 0xC0000000 - -/* - * we use the same values for 32 MB and 128 MB SDRAM - * refresh rate = 7.68 uS (100 MHz Bus Clock) - */ -#define CONFIG_SYS_MPTPR 0x2000 -#define CONFIG_SYS_PSRT 0x16 - -#define CONFIG_SYS_MRS_OFFS 0x00000000 - - -#if defined(CONFIG_BOOT_ROM) -/* - * Bank 0 - Boot ROM (8 bit wide) - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Flash (64 bit wide) - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#else /* ! CONFIG_BOOT_ROM */ - -/* - * Bank 0 - Flash (64 bit wide) - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Disk-On-Chip - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#endif /* CONFIG_BOOT_ROM */ - -/* Bank 2 - SDRAM - */ - -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL -#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */

[U-Boot,19/26] mpc8260: remove PM825, PM826, PM828 board support

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