| Message ID | 5e864091-ecd0-4a22-abbb-be8c9cd28585@EXCHANGE-4K.hds.local |
|---|---|
| State | New |
| Headers | show |
On 12/12/2014 02:10 PM, Alex Zuepke wrote: > Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> > --- > target-tricore/translate.c | 12 ++++++++++++ > target-tricore/tricore-opcodes.h | 1 + > 2 files changed, 13 insertions(+) > > diff --git a/target-tricore/translate.c b/target-tricore/translate.c > index c132223..e3eeedb 100644 > --- a/target-tricore/translate.c > +++ b/target-tricore/translate.c > @@ -3781,6 +3781,17 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, > case OPC1_32_RLC_MOV: > tcg_gen_movi_tl(cpu_gpr_d[r2], const16); > break; > + case OPC1_32_RLC_MOV_64: > + if (tricore_feature(env, TRICORE_FEATURE_16)) { > + if ((r2 & 0x1) != 0) { > + /* TODO: raise OPD trap */ > + } This reminds me, that there should be a mechanism, which can create traps for all instructions that use two 32bit regs as one 64bit one. > + tcg_gen_movi_tl(cpu_gpr_d[r2], const16); > + tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); > + } else { > + /* TODO: raise illegal opcode trap */ > + } > + break; > case OPC1_32_RLC_MOV_U: > const16 = MASK_OP_RLC_CONST16(ctx->opcode); > tcg_gen_movi_tl(cpu_gpr_d[r2], const16); > @@ -4021,6 +4032,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) > case OPC1_32_RLC_ADDIH_A: > case OPC1_32_RLC_MFCR: > case OPC1_32_RLC_MOV: > + case OPC1_32_RLC_MOV_64: > case OPC1_32_RLC_MOV_U: > case OPC1_32_RLC_MOV_H: > case OPC1_32_RLC_MOVH_A: > diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h > index 7aa6aed..a76a7e4 100644 > --- a/target-tricore/tricore-opcodes.h > +++ b/target-tricore/tricore-opcodes.h > @@ -487,6 +487,7 @@ enum { > OPC1_32_RLC_ADDIH_A = 0x11, > OPC1_32_RLC_MFCR = 0x4d, > OPC1_32_RLC_MOV = 0x3b, > + OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */ > OPC1_32_RLC_MOV_U = 0xbb, > OPC1_32_RLC_MOV_H = 0x7b, > OPC1_32_RLC_MOVH_A = 0x91, Looks good to me anyway. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index c132223..e3eeedb 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3781,6 +3781,17 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, case OPC1_32_RLC_MOV: tcg_gen_movi_tl(cpu_gpr_d[r2], const16); break; + case OPC1_32_RLC_MOV_64: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + if ((r2 & 0x1) != 0) { + /* TODO: raise OPD trap */ + } + tcg_gen_movi_tl(cpu_gpr_d[r2], const16); + tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); + } else { + /* TODO: raise illegal opcode trap */ + } + break; case OPC1_32_RLC_MOV_U: const16 = MASK_OP_RLC_CONST16(ctx->opcode); tcg_gen_movi_tl(cpu_gpr_d[r2], const16); @@ -4021,6 +4032,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPC1_32_RLC_ADDIH_A: case OPC1_32_RLC_MFCR: case OPC1_32_RLC_MOV: + case OPC1_32_RLC_MOV_64: case OPC1_32_RLC_MOV_U: case OPC1_32_RLC_MOV_H: case OPC1_32_RLC_MOVH_A: diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 7aa6aed..a76a7e4 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -487,6 +487,7 @@ enum { OPC1_32_RLC_ADDIH_A = 0x11, OPC1_32_RLC_MFCR = 0x4d, OPC1_32_RLC_MOV = 0x3b, + OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */ OPC1_32_RLC_MOV_U = 0xbb, OPC1_32_RLC_MOV_H = 0x7b, OPC1_32_RLC_MOVH_A = 0x91,
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> --- target-tricore/translate.c | 12 ++++++++++++ target-tricore/tricore-opcodes.h | 1 + 2 files changed, 13 insertions(+)