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[U-Boot,v3,24/27] x86: crownbay: Enable Intel E1000 NIC support

Message ID 1418389545-11254-25-git-send-email-bmeng.cn@gmail.com
State Superseded
Delegated to: Simon Glass
Headers show

Commit Message

Bin Meng Dec. 12, 2014, 1:05 p.m. UTC 
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2: None

 board/intel/crownbay/crownbay.c | 6 ++++++
 include/configs/crownbay.h      | 1 +
 2 files changed, 7 insertions(+)
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Patch

diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
index 54670d3..2a254ef 100644
--- a/board/intel/crownbay/crownbay.c
+++ b/board/intel/crownbay/crownbay.c
@@ -7,6 +7,7 @@ 
 #include <common.h>
 #include <asm/ibmpc.h>
 #include <asm/pnp_def.h>
+#include <netdev.h>
 #include <smsc_lpc47m.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, 4)
@@ -24,3 +25,8 @@  void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
 {
 	return;
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index a051b11..09a52ab 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -37,6 +37,7 @@ 
 
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP
+#define CONFIG_E1000
 
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \
 					"stdout=serial\0" \