| Message ID | 1418321931-12648-3-git-send-email-pbonzini@redhat.com |
|---|---|
| State | New |
| Headers | show |
diff --git a/hw/char/serial.c b/hw/char/serial.c index 4cd139f..f35fa42 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -363,12 +363,15 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, /* FIFO clear */ if (val & UART_FCR_RFR) { + s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); timer_del(s->fifo_timeout_timer); s->timeout_ipending = 0; fifo8_reset(&s->recv_fifo); } if (val & UART_FCR_XFR) { + s->lsr |= UART_LSR_THRE; + s->thr_ipending = 1; fifo8_reset(&s->xmit_fifo); }
When the transmit FIFOs is enabled, it is emptied and thus the transmitter hold register is empty. When it is disabled, the previous contents of the transmitter hold register are discarded. In either case, the THRE bit in LSR must be set and THRI raised. When the receive FIFO is enable, it is emptied and thus the data ready and break bits must be cleared in LSR. Likewise when the receive FIFO is disabled. The transmit changes fix avoid the need for thr_ipending bandaids in the routines that handle writes to IER. Without this patch, the next patch would cause a missed THRI interrupt and break the Windows COM driver. Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- hw/char/serial.c | 3 +++ 1 file changed, 3 insertions(+)