| Message ID | 3aadf6b2d0628a18c12247629a246ad9f67c513b.1418264106.git.hutao@cn.fujitsu.com |
|---|---|
| State | New |
| Headers | show |
On Thu, Dec 11, 2014 at 10:20:26AM +0800, Hu Tao wrote: > Since the limit parameter is always set to the size of pci device's > configuration space, and we can determine the size from the type of pci > device. > > Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> Not true e.g. for pci_data_read, is it? Need a bit more comments to explain why it's correct there. > --- > hw/pci/pci_host.c | 15 +++++++++++---- > hw/pci/pcie_host.c | 9 +-------- > hw/ppc/spapr_pci.c | 3 +-- > include/hw/pci/pci_host.h | 2 +- > 4 files changed, 14 insertions(+), 15 deletions(-) > > diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c > index 9bc47d8..2b11551 100644 > --- a/hw/pci/pci_host.c > +++ b/hw/pci/pci_host.c > @@ -58,12 +58,20 @@ void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, > } > > uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, > - uint32_t limit, uint32_t len) > + uint32_t len) > { > + uint32_t limit = pci_config_size(pci_dev); > uint32_t ret; > > assert(len <= 4); > - ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); > + > + if (limit <= addr) { > + /* conventional pci device can be behind pcie-to-pci bridge. > + 256 <= addr < 4K has no effects. */ > + ret = ~0x0; > + } else { > + ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); > + } > trace_pci_cfg_read(pci_dev->name, PCI_SLOT(pci_dev->devfn), > PCI_FUNC(pci_dev->devfn), addr, ret); > > @@ -95,8 +103,7 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len) > return ~0x0; > } > > - val = pci_host_config_read_common(pci_dev, config_addr, > - PCI_CONFIG_SPACE_SIZE, len); > + val = pci_host_config_read_common(pci_dev, config_addr, len); > PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n", > __func__, pci_dev->name, config_addr, val, len); > > diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c > index 3db038f..cf8587b 100644 > --- a/hw/pci/pcie_host.c > +++ b/hw/pci/pcie_host.c > @@ -62,19 +62,12 @@ static uint64_t pcie_mmcfg_data_read(void *opaque, > PCIBus *s = e->pci.bus; > PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); > uint32_t addr; > - uint32_t limit; > > if (!pci_dev) { > return ~0x0; > } > addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr); > - limit = pci_config_size(pci_dev); > - if (limit <= addr) { > - /* conventional pci device can be behind pcie-to-pci bridge. > - 256 <= addr < 4K has no effects. */ > - return ~0x0; > - } > - return pci_host_config_read_common(pci_dev, addr, limit, len); > + return pci_host_config_read_common(pci_dev, addr, len); > } > > static const MemoryRegionOps pcie_mmcfg_ops = { > diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c > index 21b95b3..59c6608 100644 > --- a/hw/ppc/spapr_pci.c > +++ b/hw/ppc/spapr_pci.c > @@ -105,8 +105,7 @@ static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid, > return; > } > > - val = pci_host_config_read_common(pci_dev, addr, > - pci_config_size(pci_dev), size); > + val = pci_host_config_read_common(pci_dev, addr, size); > > rtas_st(rets, 0, RTAS_OUT_SUCCESS); > rtas_st(rets, 1, val); > diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h > index 2bae45a..72a1b8b 100644 > --- a/include/hw/pci/pci_host.h > +++ b/include/hw/pci/pci_host.h > @@ -65,7 +65,7 @@ typedef struct PCIHostBridgeClass { > void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, > uint32_t limit, uint32_t val, uint32_t len); > uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, > - uint32_t limit, uint32_t len); > + uint32_t len); > > void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len); > uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len); > -- > 1.9.3
On Thu, Dec 11, 2014 at 10:20:26AM +0800, Hu Tao wrote: > Since the limit parameter is always set to the size of pci device's > configuration space, That's not true in case of pci_data_read, is it? While the patch might be correct, a better analysis why that's so seems called for. > and we can determine the size from the type of pci > device. > > Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> > --- > hw/pci/pci_host.c | 15 +++++++++++---- > hw/pci/pcie_host.c | 9 +-------- > hw/ppc/spapr_pci.c | 3 +-- > include/hw/pci/pci_host.h | 2 +- > 4 files changed, 14 insertions(+), 15 deletions(-) > > diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c > index 9bc47d8..2b11551 100644 > --- a/hw/pci/pci_host.c > +++ b/hw/pci/pci_host.c > @@ -58,12 +58,20 @@ void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, > } > > uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, > - uint32_t limit, uint32_t len) > + uint32_t len) > { > + uint32_t limit = pci_config_size(pci_dev); > uint32_t ret; > > assert(len <= 4); > - ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); > + > + if (limit <= addr) { > + /* conventional pci device can be behind pcie-to-pci bridge. > + 256 <= addr < 4K has no effects. */ > + ret = ~0x0; > + } else { > + ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); > + } > trace_pci_cfg_read(pci_dev->name, PCI_SLOT(pci_dev->devfn), > PCI_FUNC(pci_dev->devfn), addr, ret); > > @@ -95,8 +103,7 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len) > return ~0x0; > } > > - val = pci_host_config_read_common(pci_dev, config_addr, > - PCI_CONFIG_SPACE_SIZE, len); > + val = pci_host_config_read_common(pci_dev, config_addr, len); > PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n", > __func__, pci_dev->name, config_addr, val, len); > > diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c > index 3db038f..cf8587b 100644 > --- a/hw/pci/pcie_host.c > +++ b/hw/pci/pcie_host.c > @@ -62,19 +62,12 @@ static uint64_t pcie_mmcfg_data_read(void *opaque, > PCIBus *s = e->pci.bus; > PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); > uint32_t addr; > - uint32_t limit; > > if (!pci_dev) { > return ~0x0; > } > addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr); > - limit = pci_config_size(pci_dev); > - if (limit <= addr) { > - /* conventional pci device can be behind pcie-to-pci bridge. > - 256 <= addr < 4K has no effects. */ > - return ~0x0; > - } > - return pci_host_config_read_common(pci_dev, addr, limit, len); > + return pci_host_config_read_common(pci_dev, addr, len); > } > > static const MemoryRegionOps pcie_mmcfg_ops = { > diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c > index 21b95b3..59c6608 100644 > --- a/hw/ppc/spapr_pci.c > +++ b/hw/ppc/spapr_pci.c > @@ -105,8 +105,7 @@ static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid, > return; > } > > - val = pci_host_config_read_common(pci_dev, addr, > - pci_config_size(pci_dev), size); > + val = pci_host_config_read_common(pci_dev, addr, size); > > rtas_st(rets, 0, RTAS_OUT_SUCCESS); > rtas_st(rets, 1, val); > diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h > index 2bae45a..72a1b8b 100644 > --- a/include/hw/pci/pci_host.h > +++ b/include/hw/pci/pci_host.h > @@ -65,7 +65,7 @@ typedef struct PCIHostBridgeClass { > void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, > uint32_t limit, uint32_t val, uint32_t len); > uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, > - uint32_t limit, uint32_t len); > + uint32_t len); > > void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len); > uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len); > -- > 1.9.3
diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index 9bc47d8..2b11551 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -58,12 +58,20 @@ void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, } uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, - uint32_t limit, uint32_t len) + uint32_t len) { + uint32_t limit = pci_config_size(pci_dev); uint32_t ret; assert(len <= 4); - ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); + + if (limit <= addr) { + /* conventional pci device can be behind pcie-to-pci bridge. + 256 <= addr < 4K has no effects. */ + ret = ~0x0; + } else { + ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); + } trace_pci_cfg_read(pci_dev->name, PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn), addr, ret); @@ -95,8 +103,7 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len) return ~0x0; } - val = pci_host_config_read_common(pci_dev, config_addr, - PCI_CONFIG_SPACE_SIZE, len); + val = pci_host_config_read_common(pci_dev, config_addr, len); PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n", __func__, pci_dev->name, config_addr, val, len); diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index 3db038f..cf8587b 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -62,19 +62,12 @@ static uint64_t pcie_mmcfg_data_read(void *opaque, PCIBus *s = e->pci.bus; PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); uint32_t addr; - uint32_t limit; if (!pci_dev) { return ~0x0; } addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr); - limit = pci_config_size(pci_dev); - if (limit <= addr) { - /* conventional pci device can be behind pcie-to-pci bridge. - 256 <= addr < 4K has no effects. */ - return ~0x0; - } - return pci_host_config_read_common(pci_dev, addr, limit, len); + return pci_host_config_read_common(pci_dev, addr, len); } static const MemoryRegionOps pcie_mmcfg_ops = { diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 21b95b3..59c6608 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -105,8 +105,7 @@ static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid, return; } - val = pci_host_config_read_common(pci_dev, addr, - pci_config_size(pci_dev), size); + val = pci_host_config_read_common(pci_dev, addr, size); rtas_st(rets, 0, RTAS_OUT_SUCCESS); rtas_st(rets, 1, val); diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index 2bae45a..72a1b8b 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -65,7 +65,7 @@ typedef struct PCIHostBridgeClass { void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, uint32_t limit, uint32_t val, uint32_t len); uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, - uint32_t limit, uint32_t len); + uint32_t len); void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len); uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);
Since the limit parameter is always set to the size of pci device's configuration space, and we can determine the size from the type of pci device. Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> --- hw/pci/pci_host.c | 15 +++++++++++---- hw/pci/pcie_host.c | 9 +-------- hw/ppc/spapr_pci.c | 3 +-- include/hw/pci/pci_host.h | 2 +- 4 files changed, 14 insertions(+), 15 deletions(-)