Patchwork powerpc/swsusp_32: Fix TLB invalidation

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Submitter Anton Vorontsov
Date Dec. 30, 2009, 5:40 p.m.
Message ID <20091230174017.GA32283@oksana.dev.rtsoft.ru>
Download mbox | patch
Permalink /patch/41915/
State Accepted
Commit e443ed35606cf921cbf9d6949010a5b36bbe747d
Delegated to: Benjamin Herrenschmidt
Headers show

Comments

Anton Vorontsov - Dec. 30, 2009, 5:40 p.m.
It seems there is a thinko in the TLB invalidation code that makes the
tlbie in the loop executed just once. The intended check was probably
'gt', not 'lt'.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---

Btw, 'lis r4,0x1000' seems needlessly too high. e300 core reference
manual says:

  The [...]tlbie[...] instruction invalidates the TLB entry indexed by
  the EA, and operates on both the instruction and data TLBs
  simultaneously invalidating four TLB entries (both sets in each TLB).
  The index corresponds to bits 15-19 of the EA. To invalidate all
  entries within both TLBs, 32 tlbie instructions should be issued,
  incrementing this field by one each time.

So, shouldn't 0x1000 be 0x0002? Are there any classic PowerPCs
for which this wouldn't work?

 arch/powerpc/kernel/swsusp_32.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Patch

diff --git a/arch/powerpc/kernel/swsusp_32.S b/arch/powerpc/kernel/swsusp_32.S
index b47d8ce..b0754e2 100644
--- a/arch/powerpc/kernel/swsusp_32.S
+++ b/arch/powerpc/kernel/swsusp_32.S
@@ -303,7 +303,7 @@  END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
 	lis	r4,0x1000
 1:	addic.	r4,r4,-0x1000
 	tlbie	r4
-	blt	1b
+	bgt	1b
 	sync
 
 	/* restore the MSR and turn on the MMU */