From patchwork Tue Dec 29 15:10:58 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joakim Tjernlund X-Patchwork-Id: 41882 X-Patchwork-Delegate: benh@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 85F641007E3 for ; Wed, 30 Dec 2009 02:13:27 +1100 (EST) Received: by ozlabs.org (Postfix) id A2AE1B6EEF; Wed, 30 Dec 2009 02:13:17 +1100 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from gw1.transmode.se (gw1.transmode.se [213.115.205.20]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 487F8B6EED for ; Wed, 30 Dec 2009 02:13:17 +1100 (EST) Received: from sesr04.transmode.se (sesr04.transmode.se [192.168.201.15]) by gw1.transmode.se (Postfix) with ESMTP id 96518650002; Tue, 29 Dec 2009 16:13:12 +0100 (CET) In-Reply-To: <1260348995.16132.37.camel@pasglop> References: <1258712471-3104-1-git-send-email-Joakim.Tjernlund@transmode.se> <1258712471-3104-2-git-send-email-Joakim.Tjernlund@transmode.se> <1258712471-3104-3-git-send-email-Joakim.Tjernlund@transmode.se> <1258712471-3104-4-git-send-email-Joakim.Tjernlund@transmode.se> <1258712471-3104-5-git-send-email-Joakim.Tjernlund@transmode.se> <1260332399.16132.7.camel@pasglop> <1260348995.16132.37.camel@pasglop> Subject: Re: [PATCH 04/10] 8xx: Always pin kernel instruction TLB X-KeepSent: F526DBEE:8B45ADD7-C125769B:0053251C; type=4; name=$KeepSent To: Benjamin Herrenschmidt X-Mailer: Lotus Notes Release 8.5.1 September 28, 2009 Message-ID: From: Joakim Tjernlund Date: Tue, 29 Dec 2009 16:10:58 +0100 X-MIMETrack: Serialize by Router on sesr04/Transmode(Release 8.5.1|September 28, 2009) at 2009-12-29 16:13:12 MIME-Version: 1.0 Cc: Scott Wood , "linuxppc-dev@ozlabs.org" , Rex Feany X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Benjamin Herrenschmidt wrote on 09/12/2009 09:56:35: > From: Benjamin Herrenschmidt > To: Joakim Tjernlund > Cc: "linuxppc-dev@ozlabs.org" , Rex Feany > , Scott Wood > Date: 09/12/2009 09:56 > Subject: Re: [PATCH 04/10] 8xx: Always pin kernel instruction TLB > > On Wed, 2009-12-09 at 08:39 +0100, Joakim Tjernlund wrote: > > The later isn't as simple :) I believe the bulk of such code in > > entry_32.S. > > Yeah but it would be useful for hash I suppose if one really wants to > boot with nobats. Though at least on hash most of the time we have ways > to recover by mean of MSR:RI being cleared, which your TLB miss code > doesn't check... > > > Anyhow, the config option is still valid as if enabled > > it will pin several DTLB's too. Scott had some concerns about removing > > the config option completely so this was the next best thing. > > Well, if you want to pin at least one entry, then just remove the #if > completely but don't leave a #if 1 :-) As you wish. Here is a new version without the #if 1 This is required for 8xx to work in Linus current tree. From 5a4fa5078ba1774b037dbfd88b9c87b74cf76db7 Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Fri, 13 Nov 2009 00:26:59 +0100 Subject: [PATCH] 8xx: Always pin kernel instruction TLB Various kernel asm modifies SRR0/SRR1 just before executing a rfi. If such code crosses a page boundary you risk a TLB miss which will clobber SRR0/SRR1. Avoid this by always pinning kernel instruction TLB space. Signed-off-by: Joakim Tjernlund --- arch/powerpc/kernel/head_8xx.S | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) -- 1.6.4.4 diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index adc5a32..c80e7c5 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -767,12 +767,12 @@ start_here: */ initial_mmu: tlbia /* Invalidate all TLB entries */ -#ifdef CONFIG_PIN_TLB +/* Always pin the first 8 MB ITLB to prevent ITLB + misses while mucking around with SRR0/SRR1 in asm +*/ lis r8, MI_RSV4I@h ori r8, r8, 0x1c00 -#else - li r8, 0 -#endif + mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ #ifdef CONFIG_PIN_TLB