| Message ID | 1417610126-7957-3-git-send-email-harinik@xilinx.com |
|---|---|
| State | Accepted |
| Headers | show |
On Wed, Dec 03, 2014 at 06:05:25PM +0530, Harini Katakam wrote: > From: Vishnu Motghare <vishnum@xilinx.com> > > Cadence I2C controller has bug wherein it generates invalid read transactions > after timeout in master receiver mode. This driver does not use the HW > timeout and this interrupt is disabled but the feature itself cannot be > disabled. Hence, this patch writes the maximum value (0xFF) to this register. > This is one of the workarounds to this bug and it will not avoid the issue > completely but reduces the chances of error. > > Signed-off-by: Vishnu Motghare <vishnum@xilinx.com> > Signed-off-by: Harini Katakam <harinik@xilinx.com> Applied to for-current, thanks!
diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c index e54899e..67077c2 100644 --- a/drivers/i2c/busses/i2c-cadence.c +++ b/drivers/i2c/busses/i2c-cadence.c @@ -111,6 +111,8 @@ #define CDNS_I2C_DIVA_MAX 4 #define CDNS_I2C_DIVB_MAX 64 +#define CDNS_I2C_TIMEOUT_MAX 0xFF + #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset) #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset) @@ -858,6 +860,15 @@ static int cdns_i2c_probe(struct platform_device *pdev) goto err_clk_dis; } + /* + * Cadence I2C controller has a bug wherein it generates + * invalid read transaction after HW timeout in master receiver mode. + * HW timeout is not used by this driver and the interrupt is disabled. + * But the feature itself cannot be disabled. Hence maximum value + * is written to this register to reduce the chances of error. + */ + cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); + dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n", id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);