| Message ID | 1417481522-32110-1-git-send-email-davidu@nvidia.com |
|---|---|
| State | Rejected, archived |
| Headers | show |
Please use the scripts/get_maintainer.pl script to find the correct list of recipients. On Mon, Dec 01, 2014 at 04:52:02PM -0800, David Ung wrote: > Fixing DSI phy setting of HS trail timings. You're going to have to explain /why/ you're making this change and describe what exactly this fixes. DSI works fine on any of the boards that I have, so I'm surprised that this would need "fixing". Also: "phy" -> "PHY". > > Signed-off-by: David Ung <davidu@nvidia.com> > --- > drivers/gpu/drm/tegra/mipi-phy.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/tegra/mipi-phy.c b/drivers/gpu/drm/tegra/mipi-phy.c > index 486d19d..974bc68 100644 > --- a/drivers/gpu/drm/tegra/mipi-phy.c > +++ b/drivers/gpu/drm/tegra/mipi-phy.c > @@ -34,7 +34,7 @@ int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, > timing->hszero = 145 + 5 * period; > timing->hssettle = 85 + 6 * period; > timing->hsskip = 40; > - timing->hstrail = max(8 * period, 60 + 4 * period); > + timing->hstrail = 3 * period * 8 + max(8 * period, 60 + 4 * period); My recollection is that I took these timing values straight from the D-PHY specification, so you're going to have to explain why this is necessary and where you took this from. Thierry
> Please use the scripts/get_maintainer.pl script to find the correct list > of recipients. ccing airlied@linux.ie, tbergstrom@nvidia.com, swarren@wwwdotorg.org and gnurou@gmail.com > > Fixing DSI phy setting of HS trail timings. > > You're going to have to explain /why/ you're making this change and > describe what exactly this fixes. DSI works fine on any of the boards > that I have, so I'm surprised that this would need "fixing". It is found by hardware that after HS data burst, the HS trail is off by -12% during compliance testing. > Also: "phy" -> "PHY". I'll adjust comment. > My recollection is that I took these timing values straight from the > D-PHY specification, so you're going to have to explain why this is > necessary and where you took this from. There is set of timings recommendations in the tegra dsi programming guide. The D-PHY spec is the minimal setting, but the SOC may need other adjustments. David -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/gpu/drm/tegra/mipi-phy.c b/drivers/gpu/drm/tegra/mipi-phy.c index 486d19d..974bc68 100644 --- a/drivers/gpu/drm/tegra/mipi-phy.c +++ b/drivers/gpu/drm/tegra/mipi-phy.c @@ -34,7 +34,7 @@ int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, timing->hszero = 145 + 5 * period; timing->hssettle = 85 + 6 * period; timing->hsskip = 40; - timing->hstrail = max(8 * period, 60 + 4 * period); + timing->hstrail = 3 * period * 8 + max(8 * period, 60 + 4 * period); timing->init = 100000; timing->lpx = 60; timing->taget = 5 * timing->lpx;
Fixing DSI phy setting of HS trail timings. Signed-off-by: David Ung <davidu@nvidia.com> --- drivers/gpu/drm/tegra/mipi-phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)