From patchwork Sat Dec 19 19:45:27 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 41474 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BDE2CB6F1A for ; Sun, 20 Dec 2009 08:23:21 +1100 (EST) Received: from localhost ([127.0.0.1]:41465 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NM6li-0007b6-MN for incoming@patchwork.ozlabs.org; Sat, 19 Dec 2009 16:23:18 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NM6iM-0006ez-3F for qemu-devel@nongnu.org; Sat, 19 Dec 2009 16:19:50 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NM6iK-0006di-Id for qemu-devel@nongnu.org; Sat, 19 Dec 2009 16:19:48 -0500 Received: from [199.232.76.173] (port=49345 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NM6iJ-0006dC-JS for qemu-devel@nongnu.org; Sat, 19 Dec 2009 16:19:47 -0500 Received: from are.twiddle.net ([75.149.56.221]:45154) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NM6iI-0000g5-M5 for qemu-devel@nongnu.org; Sat, 19 Dec 2009 16:19:46 -0500 Received: by are.twiddle.net (Postfix, from userid 5000) id 10D8D8E0; Sat, 19 Dec 2009 13:19:45 -0800 (PST) Message-Id: <99efd91e465aa16579e20f7eb14d0e91c59e21c4.1261256927.git.rth@twiddle.net> In-Reply-To: References: From: Richard Henderson Date: Sat, 19 Dec 2009 11:45:27 -0800 To: qemu-devel@nongnu.org X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 2/6] tcg-sparc: Improve tcg_out_movi for sparc64. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Generate sign-extended 32-bit constants with SETHI+XOR. Otherwise tidy the routine to avoid the need for conditional compilation and code duplication with movi_imm32. --- tcg/sparc/tcg-target.c | 27 +++++++++++++++------------ 1 files changed, 15 insertions(+), 12 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index b480ed6..78b26c9 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -314,22 +314,25 @@ static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg) static inline void tcg_out_movi(TCGContext *s, TCGType type, int ret, tcg_target_long arg) { -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) - if (!check_fit_tl(arg, 32) && (arg & ~0xffffffffULL) != 0) { - tcg_out_movi_imm32(s, TCG_REG_I4, arg >> 32); + /* All 32-bit constants, as well as 64-bit constants with + no high bits set go through movi_imm32. */ + if (TCG_TARGET_REG_BITS == 32 + || type == TCG_TYPE_I32 + || (arg & ~(tcg_target_long)0xffffffff) == 0) { + tcg_out_movi_imm32(s, ret, arg); + } else if (check_fit_tl(arg, 13)) { + /* A 13-bit constant sign-extended to 64-bits. */ + tcg_out_movi_imm13(s, ret, arg); + } else if (check_fit_tl(arg, 32)) { + /* A 32-bit constant sign-extended to 64-bits. */ + tcg_out_sethi(s, ret, ~arg); + tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); + } else { + tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2)); tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX); tcg_out_movi_imm32(s, ret, arg); tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR); - } else if (check_fit_tl(arg, 12)) - tcg_out_movi_imm13(s, ret, arg); - else { - tcg_out_sethi(s, ret, arg); - if (arg & 0x3ff) - tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); } -#else - tcg_out_movi_imm32(s, ret, arg); -#endif } static inline void tcg_out_ld_raw(TCGContext *s, int ret,