diff mbox

[U-Boot,v2,2/5] serial: pl01x: fix pl011 baud rate configuration

Message ID 1416594863-16466-3-git-send-email-vikas.manocha@st.com
State Accepted
Delegated to: Tom Rini
Headers show

Commit Message

Vikas MANOCHA Nov. 21, 2014, 6:34 p.m. UTC 
UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which
is updated on a single write strobe generated by a UART_LCR_H write. So, to
internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H
must always be performed at the end.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- fixed comment style

 drivers/serial/serial_pl01x.c |    8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Tom Rini Dec. 8, 2014, 9:42 p.m. UTC | #1 
On Fri, Nov 21, 2014 at 10:34:20AM -0800, Vikas Manocha wrote:

> UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which
> is updated on a single write strobe generated by a UART_LCR_H write. So, to
> internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H
> must always be performed at the end.
> 
> Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot/master, thanks!
diff mbox

Patch

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 1860289..a58ad8a 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -122,6 +122,7 @@  static int pl01x_generic_serial_init(struct pl01x_regs *regs,
 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 				int clock, int baudrate)
 {
+	unsigned int lcr;
 	switch (type) {
 	case TYPE_PL010: {
 		unsigned int divisor;
@@ -175,6 +176,13 @@  static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 		writel(divider, &regs->pl011_ibrd);
 		writel(fraction, &regs->pl011_fbrd);
 
+		/*
+		 * Internal update of baud rate register require line
+		 * control register write
+		 */
+		lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
+		writel(lcr, &regs->pl011_lcrh);
+
 		/* Finally, enable the UART */
 		writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
 		       UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);