diff mbox

[AArch64,4/5] Implement fusion of ARDP+LDR

Message ID 546B2093.8060406@arm.com
State New
Headers show

Commit Message

Kyrylo Tkachov Nov. 18, 2014, 10:33 a.m. UTC 
Hi all,

Sometimes we want to fuse adrp+ldr pairs as described in the comment in 
the patch.
This is enabled by default for the Cortex-A53.

Bootstrapped and tested on aarch64-none-linux.

Ok for trunk?

Thanks,
Kyrill

2014-11-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/aarch64/aarch64.c (AARCH64_FUSE_ADRP_LDR): Define.
     (cortexa53_tunings): Specify AARCH64_FUSE_ADRP_LDR in fuseable_ops.
     (aarch_macro_fusion_pair_p): Handle AARCH64_FUSE_ADRP_LDR.

Comments

Marcus Shawcroft Nov. 21, 2014, 4:58 p.m. UTC | #1 
On 18 November 2014 10:33, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote:

> 2014-11-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>     * config/aarch64/aarch64.c (AARCH64_FUSE_ADRP_LDR): Define.
>     (cortexa53_tunings): Specify AARCH64_FUSE_ADRP_LDR in fuseable_ops.
>     (aarch_macro_fusion_pair_p): Handle AARCH64_FUSE_ADRP_LDR.

OK /Marcus
diff mbox

Patch

commit ad175271f82e0330894bfe894e86f7ad8a4b6cce
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu Nov 13 16:48:18 2014 +0000

    [AArch64][tmp] Fuse ADRP+LDR

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 85e08d0..132535c 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -307,6 +307,7 @@  static const struct cpu_vector_cost cortexa57_vector_cost =
 #define AARCH64_FUSE_MOV_MOVK	(1 << 0)
 #define AARCH64_FUSE_ADRP_ADD	(1 << 1)
 #define AARCH64_FUSE_MOVK_MOVK	(1 << 2)
+#define AARCH64_FUSE_ADRP_LDR	(1 << 3)
 
 #if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
 __extension__
@@ -330,7 +331,8 @@  static const struct tune_params cortexa53_tunings =
   &generic_vector_cost,
   NAMED_PARAM (memmov_cost, 4),
   NAMED_PARAM (issue_rate, 2),
-  NAMED_PARAM (fuseable_ops, (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD | AARCH64_FUSE_MOVK_MOVK))
+  NAMED_PARAM (fuseable_ops, (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+                             | AARCH64_FUSE_MOVK_MOVK | AARCH64_FUSE_ADRP_LDR))
 };
 
 static const struct tune_params cortexa57_tunings =
@@ -10467,6 +10469,37 @@  aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
         return true;
 
     }
+  if (simple_sets_p
+      && (aarch64_tune_params->fuseable_ops & AARCH64_FUSE_ADRP_LDR))
+    {
+      /* We're trying to match:
+          prev (adrp) == (set (reg r0)
+                              (high (symbol_ref ("SYM"))))
+          curr (ldr) == (set (reg r1)
+                             (mem (lo_sum (reg r0)
+                                             (symbol_ref ("SYM")))))
+                 or
+          curr (ldr) == (set (reg r1)
+                             (zero_extend (mem
+                                           (lo_sum (reg r0)
+                                                   (symbol_ref ("SYM"))))))  */
+      if (satisfies_constraint_Ush (SET_SRC (prev_set))
+          && REG_P (SET_DEST (prev_set)) && REG_P (SET_DEST (curr_set)))
+        {
+          rtx curr_src = SET_SRC (curr_set);
+
+          if (GET_CODE (curr_src) == ZERO_EXTEND)
+            curr_src = XEXP (curr_src, 0);
+
+          if (MEM_P (curr_src) && GET_CODE (XEXP (curr_src, 0)) == LO_SUM
+              && REG_P (XEXP (XEXP (curr_src, 0), 0))
+              && REGNO (XEXP (XEXP (curr_src, 0), 0))
+                 == REGNO (SET_DEST (prev_set))
+              && rtx_equal_p (XEXP (XEXP (curr_src, 0), 1),
+                              XEXP (SET_SRC (prev_set), 0)))
+              return true;
+        }
+    }
 
   return false;
 }