From patchwork Mon Dec 14 11:09:13 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: correcting ARM CPSR register bit position comment Date: Mon, 14 Dec 2009 01:09:13 -0000 From: nemesisofstate X-Patchwork-Id: 41085 Message-Id: <1260788953-30794-1-git-send-email-nemesisofstate@gmail.com> To: qemu-devel@nongnu.org From: nemesis --- target-arm/cpu.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4a1c53f..910604f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -90,7 +90,7 @@ typedef struct CPUARMState { /* cpsr flag cache for faster execution */ uint32_t CF; /* 0 or 1 */ - uint32_t VF; /* V is the bit 31. All other bits are undefined */ + uint32_t VF; /* V is the bit 28. */ uint32_t NF; /* N is bit 31. All other bits are undefined. */ uint32_t ZF; /* Z set if zero. */ uint32_t QF; /* 0 or 1 */