Patchwork correcting ARM CPSR register bit position comment

login
register
mail settings
Submitter nemesisofstate
Date Dec. 14, 2009, 11:09 a.m.
Message ID <1260788953-30794-1-git-send-email-nemesisofstate@gmail.com>
Download mbox | patch
Permalink /patch/41085/
State New
Headers show

Comments

nemesisofstate - Dec. 14, 2009, 11:09 a.m.
From: nemesis <nemesis@nemesis-laptop.(none)>

---
 target-arm/cpu.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
Paul Brook - Dec. 14, 2009, 12:07 p.m.
> -    uint32_t VF; /* V is the bit 31. All other bits are undefined */
> +    uint32_t VF; /* V is the bit 28. */

No. The original comment is correct.

Paul
Laurent Desnogues - Dec. 14, 2009, 12:15 p.m.
On Mon, Dec 14, 2009 at 1:07 PM, Paul Brook <paul@codesourcery.com> wrote:
>> -    uint32_t VF; /* V is the bit 31. All other bits are undefined */
>> +    uint32_t VF; /* V is the bit 28. */
>
> No. The original comment is correct.

And so that the answer is at least a bit useful:  these fields
are not directly mapped to CPSR;  they are the results of
computations and can then be translated to bits in CPSR
(look for cpsr_read/cpsr_write in helper.c).  If you want to
see how VF is set, look for add_cc in op_helper.c.  This is
done this way to speed up simulation.

HTH,

Laurent

Patch

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4a1c53f..910604f 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -90,7 +90,7 @@  typedef struct CPUARMState {
 
     /* cpsr flag cache for faster execution */
     uint32_t CF; /* 0 or 1 */
-    uint32_t VF; /* V is the bit 31. All other bits are undefined */
+    uint32_t VF; /* V is the bit 28. */
     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
     uint32_t ZF; /* Z set if zero.  */
     uint32_t QF; /* 0 or 1 */