Message ID | 1415857349-14653-11-git-send-email-sjg@chromium.org |
---|---|
State | Accepted |
Delegated to: | Simon Glass |
Headers | show |
On 13 November 2014 06:42, Simon Glass <sjg@chromium.org> wrote: > Enable PCI so we can access devices that need to be set up before relocation. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > Changes in v3: > - Adjust PCI setup code to fit with new generic cpu PCI code > > Changes in v2: None > > arch/x86/cpu/ivybridge/Makefile | 1 + > arch/x86/cpu/ivybridge/cpu.c | 6 ++++ > arch/x86/cpu/ivybridge/pci.c | 60 +++++++++++++++++++++++++++++++++++++++ > include/configs/chromebook_link.h | 14 +++++++-- > 4 files changed, 79 insertions(+), 2 deletions(-) > create mode 100644 arch/x86/cpu/ivybridge/pci.c Applied to u-boot-x86.
Hello Simon, Is there a specific case to use PCI before relocation? Or it only applies for x86? If so, we could figure out how to use this new feature. Thanks for the info. Regards, James > Date: Fri, 21 Nov 2014 07:51:08 +0100 > From: sjg@chromium.org > To: u-boot@lists.denx.de > CC: graeme.russ@gmail.com > Subject: Re: [U-Boot] [PATCH v3 10/26] x86: ivybridge: Enable PCI in early init > > On 13 November 2014 06:42, Simon Glass <sjg@chromium.org> wrote: > > Enable PCI so we can access devices that need to be set up before relocation. > > > > Signed-off-by: Simon Glass <sjg@chromium.org> > > --- > > > > Changes in v3: > > - Adjust PCI setup code to fit with new generic cpu PCI code > > > > Changes in v2: None > > > > arch/x86/cpu/ivybridge/Makefile | 1 + > > arch/x86/cpu/ivybridge/cpu.c | 6 ++++ > > arch/x86/cpu/ivybridge/pci.c | 60 +++++++++++++++++++++++++++++++++++++++ > > include/configs/chromebook_link.h | 14 +++++++-- > > 4 files changed, 79 insertions(+), 2 deletions(-) > > create mode 100644 arch/x86/cpu/ivybridge/pci.c > > Applied to u-boot-x86. > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot
HI James, On 24 November 2014 at 00:06, James Zhou <james.zhou.link@outlook.com> wrote: > Hello Simon, > > Is there a specific case to use PCI before relocation? > Or it only applies for x86? > If so, we could figure out how to use this new feature. Thanks for the info. It's not x86-specific - you can use this for any arch. The main enabler was pre-relocation malloc() which is now supported in U-Boot. Regards, Simon > > Regards, > James > >> Date: Fri, 21 Nov 2014 07:51:08 +0100 >> From: sjg@chromium.org >> To: u-boot@lists.denx.de >> CC: graeme.russ@gmail.com >> Subject: Re: [U-Boot] [PATCH v3 10/26] x86: ivybridge: Enable PCI in early >> init > >> >> On 13 November 2014 06:42, Simon Glass <sjg@chromium.org> wrote: >> > Enable PCI so we can access devices that need to be set up before >> > relocation. >> > >> > Signed-off-by: Simon Glass <sjg@chromium.org> >> > --- >> > >> > Changes in v3: >> > - Adjust PCI setup code to fit with new generic cpu PCI code >> > >> > Changes in v2: None >> > >> > arch/x86/cpu/ivybridge/Makefile | 1 + >> > arch/x86/cpu/ivybridge/cpu.c | 6 ++++ >> > arch/x86/cpu/ivybridge/pci.c | 60 >> > +++++++++++++++++++++++++++++++++++++++ >> > include/configs/chromebook_link.h | 14 +++++++-- >> > 4 files changed, 79 insertions(+), 2 deletions(-) >> > create mode 100644 arch/x86/cpu/ivybridge/pci.c >> >> Applied to u-boot-x86. >> _______________________________________________ >> U-Boot mailing list >> U-Boot@lists.denx.de >> http://lists.denx.de/mailman/listinfo/u-boot
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index dbcd4bd..6d0a78d 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -6,4 +6,5 @@ obj-y += car.o obj-y += cpu.o +obj-y += pci.o obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 5863811..ff6b7b3 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -12,6 +12,7 @@ #include <common.h> #include <asm/cpu.h> +#include <asm/pci.h> #include <asm/post.h> #include <asm/processor.h> @@ -19,6 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; int arch_cpu_init(void) { + struct pci_controller *hose; int ret; post_code(POST_CPU_INIT); @@ -28,6 +30,10 @@ int arch_cpu_init(void) if (ret) return ret; + ret = pci_early_init_hose(&hose); + if (ret) + return ret; + return 0; } diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c new file mode 100644 index 0000000..c1ae658 --- /dev/null +++ b/arch/x86/cpu/ivybridge/pci.c @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008,2009 + * Graeme Russ, <graeme.russ@gmail.com> + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <pci.h> +#include <asm/pci.h> + +static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *table) +{ + u8 secondary; + + hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); + if (secondary != 0) + pci_hose_scan_bus(hose, secondary); +} + +static struct pci_config_table pci_ivybridge_config_table[] = { + /* vendor, device, class, bus, dev, func */ + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, + {} +}; + +void board_pci_setup_hose(struct pci_controller *hose) +{ + hose->config_table = pci_ivybridge_config_table; + hose->first_busno = 0; + hose->last_busno = 0; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); + + hose->region_count = 3; +} diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 3137ef0..0b8c067 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -45,8 +45,6 @@ #undef CONFIG_CMD_GPIO #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE -#undef CONFIG_SYS_EARLY_PCI_INIT -#undef CONFIG_PCI #undef CONFIG_ICH_SPI #undef CONFIG_SPI #undef CONFIG_CMD_SPI @@ -55,6 +53,18 @@ #undef CONFIG_CMD_USB #undef CONFIG_CMD_SCSI +#define CONFIG_PCI_MEM_BUS 0xe0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xd0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x1000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xefff + #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial\0" \ "stderr=vga,serial\0"
Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v3: - Adjust PCI setup code to fit with new generic cpu PCI code Changes in v2: None arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/cpu.c | 6 ++++ arch/x86/cpu/ivybridge/pci.c | 60 +++++++++++++++++++++++++++++++++++++++ include/configs/chromebook_link.h | 14 +++++++-- 4 files changed, 79 insertions(+), 2 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/pci.c