From patchwork Sat Dec 12 20:57:22 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artyom Tarasenko X-Patchwork-Id: 40993 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1CB32B6F16 for ; Sun, 13 Dec 2009 07:58:27 +1100 (EST) Received: from localhost ([127.0.0.1]:56590 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NJZ2m-0006pz-2x for incoming@patchwork.ozlabs.org; Sat, 12 Dec 2009 15:58:24 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NJZ1v-0006ad-U3 for qemu-devel@nongnu.org; Sat, 12 Dec 2009 15:57:31 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NJZ1r-0006WO-2h for qemu-devel@nongnu.org; Sat, 12 Dec 2009 15:57:31 -0500 Received: from [199.232.76.173] (port=39137 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NJZ1q-0006WD-Q2 for qemu-devel@nongnu.org; Sat, 12 Dec 2009 15:57:26 -0500 Received: from mail-fx0-f219.google.com ([209.85.220.219]:56360) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NJZ1q-0003V8-BZ for qemu-devel@nongnu.org; Sat, 12 Dec 2009 15:57:26 -0500 Received: by fxm19 with SMTP id 19so2034934fxm.17 for ; Sat, 12 Dec 2009 12:57:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=16nxeqfj8RJz4hSAsuNTUXOvZYWYB2C67UnHG2OTV2Q=; b=QBZyUXOtq3/1ZpRAx2TmBqe6/w+ahduX6ERrKgI33mq74yNhLHwrO4ZrZ5R9P1n5Ku HSHIDIc6dD+a6uLVkD5rTjT5by13IKHBX6qctkq03q64rdS5Fja60NQNC18xk7ewLpvm iCTxXXzspKC+TL5cseDru/UREANjCdJqh201Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=KffxA3jN/c8P0hDP1Gjd/4O64I0Urn8BxotAZnR5yWNRwXYyOicMksAvsRw4aoVI8T QSBVXd7lqQ2S1E9EjQdyQmZ4NWWMTh/ZOAtOcZfTwhqTiINHOXaEsdGH4lrr7e2eb13M FLLDVUYXhPTaabNFldx35dJ8rMZgSEV4jzipk= Received: by 10.223.4.216 with SMTP id 24mr3251945fas.67.1260651445269; Sat, 12 Dec 2009 12:57:25 -0800 (PST) Received: from localhost (e181216067.adsl.alicedsl.de [85.181.216.67]) by mx.google.com with ESMTPS id 22sm4857452fkq.24.2009.12.12.12.57.23 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 12 Dec 2009 12:57:24 -0800 (PST) From: Artyom Tarasenko To: "qemu-devel" Date: Sat, 12 Dec 2009 21:57:22 +0100 Message-Id: <1260651442-14085-1-git-send-email-atar4qemu@google.com> X-Mailer: git-send-email 1.6.2.5 X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: Blue Swirl , Artyom Tarasenko Subject: [Qemu-devel] [FOR 0.12 PATCH] sparc implement AFX for SS-5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implement a stub for the AFX register on SparcStation-5. This stub is needed for running the original SS-5 OBP instead of OpenBIOS (which allows to boot Solaris 2.5.1 and Solaris 2.6 kernels). --- Signed-off-by: Artyom Tarasenko --- diff --git a/hw/sun4m.c b/hw/sun4m.c index 5b3e0fd..7db00b8 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -95,7 +95,7 @@ struct sun4m_hwdef { target_phys_addr_t iommu_base, slavio_base; target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; target_phys_addr_t serial_base, fd_base; - target_phys_addr_t idreg_base, dma_base, esp_base, le_base; + target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base; target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; target_phys_addr_t ecc_base; uint32_t ecc_version; @@ -600,6 +600,41 @@ static void idreg_register_devices(void) device_init(idreg_register_devices); +/* SS-5 TCX AFX register */ +static void afx_init(target_phys_addr_t addr) +{ + DeviceState *dev; + SysBusDevice *s; + + dev = qdev_create(NULL, "tcx_afx"); + qdev_init_nofail(dev); + s = sysbus_from_qdev(dev); + + sysbus_mmio_map(s, 0, addr); +} + +static int afx_init1(SysBusDevice *dev) +{ + ram_addr_t afx_offset; + + afx_offset = qemu_ram_alloc(4); + sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM); + return 0; +} + +static SysBusDeviceInfo afx_info = { + .init = afx_init1, + .qdev.name = "tcx_afx", + .qdev.size = sizeof(SysBusDevice), +}; + +static void afx_register_devices(void) +{ + sysbus_register_withprop(&afx_info); +} + +device_init(afx_register_devices); + /* Boot PROM (OpenBIOS) */ static void prom_init(target_phys_addr_t addr, const char *bios_name) { @@ -795,6 +830,10 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, idreg_init(hwdef->idreg_base); } + if (hwdef->afx_base) { + afx_init(hwdef->afx_base); + } + iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); @@ -920,6 +959,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .esp_base = 0x78800000, .le_base = 0x78c00000, .apc_base = 0x6a000000, + .afx_base = 0x6e000000, .aux1_base = 0x71900000, .aux2_base = 0x71910000, .nvram_machine_id = 0x80,