@@ -17,3 +17,4 @@ obj-y += pci.o
obj-y += report_platform.o
obj-y += sata.o
obj-y += sdram.o
+obj-y += usb_ehci.o
@@ -102,6 +102,8 @@ int bd82x6x_init_pci_devices(void)
return -EINVAL;
}
bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
+ bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
+ bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
return 0;
}
new file mode 100644
@@ -0,0 +1,29 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+void bd82x6x_usb_ehci_init(pci_dev_t dev)
+{
+ u32 reg32;
+
+ /* Disable Wake on Disconnect in RMH */
+ reg32 = readl(RCB_REG(0x35b0));
+ reg32 |= 0x22;
+ writel(reg32, RCB_REG(0x35b0));
+
+ debug("EHCI: Setting up controller.. ");
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER;
+ /* reg32 |= PCI_COMMAND_SERR; */
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ debug("done.\n");
+}
@@ -10,6 +10,7 @@
void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
void bd82x6x_pci_init(pci_dev_t dev);
+void bd82x6x_usb_ehci_init(pci_dev_t dev);
int bd82x6x_init_pci_devices(void);
int bd82x6x_init(void);
Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org> --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 2 ++ arch/x86/cpu/ivybridge/usb_ehci.c | 29 +++++++++++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 + 4 files changed, 33 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c