Patchwork [04/17] pcnet: switch to symbolic names for pci registers

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Submitter Michael S. Tsirkin
Date Dec. 10, 2009, 6:10 p.m.
Message ID <20091210181003.GE25707@redhat.com>
Download mbox | patch
Permalink /patch/40854/
State New
Headers show

Comments

Michael S. Tsirkin - Dec. 10, 2009, 6:10 p.m.
No functional changes. I verified that the generated binary
does not change.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/pci.h   |    1 +
 hw/pcnet.c |   26 +++++++++++++++++---------
 2 files changed, 18 insertions(+), 9 deletions(-)

Patch

diff --git a/hw/pci.h b/hw/pci.h
index d279e3f..dd61fa1 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -165,6 +165,7 @@  typedef struct PCIIORegion {
 #define PCI_STATUS_66MHZ	0x020
 #define PCI_STATUS_RESERVED2	0x040
 #define PCI_STATUS_FAST_BACK	0x080
+#define PCI_STATUS_DEVSEL_MEDIUM 0x200
 #define PCI_STATUS_DEVSEL	0x600
 
 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
diff --git a/hw/pcnet.c b/hw/pcnet.c
index 138fbc6..91d106d 100644
--- a/hw/pcnet.c
+++ b/hw/pcnet.c
@@ -1981,24 +1981,32 @@  static int pci_pcnet_init(PCIDevice *pci_dev)
 
     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_AMD);
     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_AMD_LANCE);
-    *(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007);
-    *(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);
-    pci_conf[0x08] = 0x10;
-    pci_conf[0x09] = 0x00;
+    /* TODO: value should be 0 at RST# */
+    pci_set_word(pci_conf + PCI_COMMAND,
+                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+    pci_set_word(pci_conf + PCI_STATUS,
+                 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
+    pci_conf[PCI_REVISION_ID] = 0x10;
+    /* TODO: 0 is the default anyway, no need to set it. */
+    pci_conf[PCI_CLASS_PROG] = 0x00;
     pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 
-    *(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);
-    *(uint32_t *)&pci_conf[0x14] = cpu_to_le32(0x00000000);
+    /* TODO: not necessary, is set when BAR is registered. */
+    pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_IO);
+    pci_set_long(pci_conf + PCI_BASE_ADDRESS_0 + 4,
+                 PCI_BASE_ADDRESS_SPACE_MEMORY);
 
-    pci_conf[0x3d] = 1; // interrupt pin 0
-    pci_conf[0x3e] = 0x06;
-    pci_conf[0x3f] = 0xff;
+    /* TODO: value must be 0 at RST# */
+    pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
+    pci_conf[PCI_MIN_GNT] = 0x06;
+    pci_conf[PCI_MAX_LAT] = 0xff;
 
     /* Handler for memory-mapped I/O */
     s->mmio_index =
       cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state);
 
+    /* TODO: use pci_dev, avoid cast below. */
     pci_register_bar((PCIDevice *)d, 0, PCNET_IOPORT_SIZE,
                            PCI_BASE_ADDRESS_SPACE_IO, pcnet_ioport_map);