From patchwork Tue Dec 8 18:01:01 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nathan Froyd X-Patchwork-Id: 40665 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 882CFB7BCC for ; Wed, 9 Dec 2009 05:56:04 +1100 (EST) Received: from localhost ([127.0.0.1]:52840 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NI5E9-0006Rg-J6 for incoming@patchwork.ozlabs.org; Tue, 08 Dec 2009 13:56:01 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NI4N3-0001B3-7o for qemu-devel@nongnu.org; Tue, 08 Dec 2009 13:01:09 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NI4My-00015G-Lr for qemu-devel@nongnu.org; Tue, 08 Dec 2009 13:01:08 -0500 Received: from [199.232.76.173] (port=34041 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NI4My-000156-FJ for qemu-devel@nongnu.org; Tue, 08 Dec 2009 13:01:04 -0500 Received: from mx20.gnu.org ([199.232.41.8]:57667) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NI4My-0005kG-5P for qemu-devel@nongnu.org; Tue, 08 Dec 2009 13:01:04 -0500 Received: from mail.codesourcery.com ([38.113.113.100]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NI4Mw-0006Z2-WF for qemu-devel@nongnu.org; Tue, 08 Dec 2009 13:01:03 -0500 Received: (qmail 5944 invoked from network); 8 Dec 2009 18:01:01 -0000 Received: from unknown (HELO localhost) (froydnj@127.0.0.2) by mail.codesourcery.com with ESMTPA; 8 Dec 2009 18:01:01 -0000 Date: Tue, 8 Dec 2009 10:01:01 -0800 From: Nathan Froyd To: qemu-devel@nongnu.org Subject: Re: [Qemu-devel] [PATCH 05/11] target-mips: add gen_base_offset_addr Message-ID: <20091208180100.GB32389@codesourcery.com> References: <1260288392-20804-1-git-send-email-froydnj@codesourcery.com> <1260288392-20804-6-git-send-email-froydnj@codesourcery.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1260288392-20804-6-git-send-email-froydnj@codesourcery.com> User-Agent: Mutt/1.5.13 (2006-08-11) X-detected-operating-system: by mx20.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This is a common pattern in existing code. We'll also use it to implement the mips16 SAVE/RESTORE instructions. Signed-off-by: Nathan Froyd --- Argh, please use this one instead; the arguments passed to gen_op_addr_add in gen_base_offset_addr are in the "proper" order. target-mips/translate.c | 40 ++++++++++++++++------------------------ 1 files changed, 16 insertions(+), 24 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 3751516..b38b97f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -981,6 +981,19 @@ OP_ST_ATOMIC(scd,st64,ld64,0x7); #endif #undef OP_ST_ATOMIC +static void gen_base_offset_addr (DisasContext *ctx, TCGv addr, + int base, int16_t offset) +{ + if (base == 0) { + tcg_gen_movi_tl(addr, offset); + } else if (offset == 0) { + gen_load_gpr(addr, base); + } else { + tcg_gen_movi_tl(addr, offset); + gen_op_addr_add(ctx, addr, cpu_gpr[base], addr); + } +} + /* Load and store */ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, int base, int16_t offset) @@ -989,14 +1002,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); - if (base == 0) { - tcg_gen_movi_tl(t0, offset); - } else if (offset == 0) { - gen_load_gpr(t0, base); - } else { - tcg_gen_movi_tl(t0, offset); - gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); - } + gen_base_offset_addr(ctx, t0, base, offset); /* Don't do NOP if destination is zero: we must perform the actual memory access. */ switch (opc) { @@ -1147,14 +1153,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, t0 = tcg_temp_local_new(); - if (base == 0) { - tcg_gen_movi_tl(t0, offset); - } else if (offset == 0) { - gen_load_gpr(t0, base); - } else { - tcg_gen_movi_tl(t0, offset); - gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); - } + gen_base_offset_addr(ctx, t0, base, offset); /* Don't do NOP if destination is zero: we must perform the actual memory access. */ @@ -1186,14 +1185,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, const char *opn = "flt_ldst"; TCGv t0 = tcg_temp_new(); - if (base == 0) { - tcg_gen_movi_tl(t0, offset); - } else if (offset == 0) { - gen_load_gpr(t0, base); - } else { - tcg_gen_movi_tl(t0, offset); - gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); - } + gen_base_offset_addr(ctx, t0, base, offset); /* Don't do NOP if destination is zero: we must perform the actual memory access. */ switch (opc) {