diff --git a/hw/barriers.h b/hw/barriers.h
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--- /dev/null
+++ b/hw/barriers.h
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+/*
+ * Copyright (c) 2005 Topspin Communications.  All rights reserved.
+ * Copyright (c) 2009 Red Hat Inc.  All rights reserved.
+ *
+ * Author: Michael S. Tsirkin <mst@redhat.com>
+ * Based on libibverbs library by Roland Dreier <rolandd@cisco.com>
+ *
+ * Note: Please be nice and keep the BSD license option on this file around, so
+ * that libibverbs library can reuse this code if it wants to.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef QEMU_BARRIERS_H
+#define QEMU_BARRIERS_H
+
+/* Compiler barrier. Prevents compiler from re-ordering
+ * memory operations, but does not prevent CPU from doing this. */
+#define barrier() asm volatile("" ::: "memory")
+
+/*
+ * Host-architecture-specific defines.  Currently, an architecture is
+ * required to implement the following operations:
+ *
+ * mb() - memory barrier.  No loads or stores may be reordered across
+ *     this macro by either the compiler or the CPU.
+ * rmb() - read memory barrier.  No loads may be reordered across this
+ *     macro by either the compiler or the CPU.
+ * wmb() - write memory barrier.  No stores may be reordered across
+ *     this macro by either the compiler or the CPU.
+ */
+
+#if defined(__i386__)
+
+/* We use GCC builtin if it's available, as that can use
+ * mfence on 32 bit as well, e.g. if built with -march=pentium-m.
+ * However, on i386, there seem to be known bugs as recently as 4.3. */
+#if defined(_GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 4
+#define mb() __sync_synchronize()
+#else
+#define mb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
+#endif
+#define rmb() mb()
+/*
+ * We use a compiler barrier for wmb() because we don't care about
+ * ordering against non-temporal/string stores (for now at least).
+ */
+#define wmb() barrier()
+
+#elif defined(__x86_64__)
+
+/*
+ * We use a compiler barrier for wmb() because we don't care about
+ * ordering against non-temporal/string stores (for now at least).
+ */
+#define mb() asm volatile("mfence" ::: "memory")
+#define rmb() asm volatile("lfence" ::: "memory")
+#define wmb() barrier()
+
+#elif defined(__PPC64__)
+
+#define mb() asm volatile("sync" ::: "memory")
+#define rmb() asm volatile("lwsync" ::: "memory")
+#define wmb() mb()
+
+#elif defined(__ia64__)
+
+#define mb() asm volatile("mf" ::: "memory")
+#define rmb() mb()
+#define wmb() mb()
+
+#elif defined(__PPC__)
+
+#define mb() asm volatile("sync" ::: "memory")
+#define rmb() mb()
+#define wmb() asm volatile("eieio" ::: "memory")
+
+#elif defined(__sparc_v9__)
+
+#define mb() asm volatile("membar #LoadLoad | #LoadStore | " \
+                          "#StoreStore | #StoreLoad" ::: "memory")
+#define rmb() asm volatile("membar #LoadLoad" ::: "memory")
+#define wmb() asm volatile("membar #StoreStore" ::: "memory")
+
+#elif defined(__sparc__)
+
+#define mb() barrier()
+#define rmb() mb()
+#define wmb() mb()
+
+#else
+
+#warning No architecture specific defines found.  Using generic implementation.
+
+/* Use GCC builtin if it's available. */
+#if defined(_GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 1
+#define mb() __sync_synchronize()
+#else
+#define mb() barrier()
+#endif
+#define rmb() mb()
+#define wmb() mb()
+
+#endif
+#endif /* QEMU_BARRIERS_H */