| Message ID | 1414745754-4394-5-git-send-email-akshay.s@samsung.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Minkyu Kang |
| Headers | show |
On 31 October 2014 02:55, Akshay Saraswat <akshay.s@samsung.com> wrote: > From: Alim Akhtar <alim.akhtar@samsung.com> > > As per Exynos5800 UM ver 0.00 section 17.13.2.1 > CONCONTROL register bit 3 [update_mode], Exynos5800 does not > support the PHY initiated update. And it is recommanded to > set this field to 1'b1 during initialization. This patch sets this bit. > Applying MC-initiated mode makes DDL tracking ON, that helps in > compensate MIF voltage variation. > > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> > Signed-off-by: Doug Anderson <dianders@chromium.org> > Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> > --- > Changes since v2: > - Rebased this patch > > Changes since v1: > - Rebased this patch > > arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 19 +++++++++++++++++++ > arch/arm/include/asm/arch-exynos/dmc.h | 1 + > 2 files changed, 20 insertions(+) > Acked-by: Simon Glass <sjg@chromium.org> Tested on Pi: Tested-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index b86dd2d..4d73b45 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -832,6 +832,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG); setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG); + /* + * As per Exynos5800 UM ver 0.00 section 17.13.2.1 + * CONCONTROL register bit 3 [update_mode], Exynos5800 does not + * support the PHY initiated update. And it is recommended to set + * this field to 1'b1 during initialization + * + * When we apply PHY-initiated mode, DLL lock value is determined + * once at DMC init time and not updated later when we change the MIF + * voltage based on ASV group in kernel. Applying MC-initiated mode + * makes sure that DLL tracing is ON so that silicon is able to + * compensate the voltage variation. + */ + val = readl(&drex0->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex0->concontrol); + val = readl(&drex1->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex1->concontrol); + return 0; } #endif diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index ec3f9b6..4990a1a 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -450,6 +450,7 @@ enum mem_manuf { #define CONCONTROL_RD_FETCH_SHIFT 12 #define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) #define CONCONTROL_AREF_EN_SHIFT 5 +#define CONCONTROL_UPDATE_MODE (1 << 3) /* PRECHCONFIG register field */ #define PRECHCONFIG_TP_CNT_SHIFT 24