[MIPS] Add Octeon3 support

Message ID	1414738195329.46236@caviumnetworks.com
State	New
Headers	show Return-Path: <gcc-patches-return-382477-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:mime-version; q=dns; s=default; b=YPSyuv0UrMq7GN0t zgg7wvbdviuCyrhTqjgHhbP2KBx0gYDOpnXckQdpSL6PGyzg3iOGARGdzBkeeC82 g+ECKayrLttOLxrHcwgwvVSXOdeqFMNpT5hofpbpI0kv4bx4nCygeIUS1aYR0Xlg QhVF8iCDOHS0Y2fqhWjHTxmmvOQ= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: "Hurugalawadi, Naveen" <Naveen.Hurugalawadi@caviumnetworks.com> To: "Moore, Catherine" <Catherine_Moore@mentor.com>, Matthew Fortune <Matthew.Fortune@imgtec.com>, "Myers, Joseph" <joseph_myers@mentor.com> CC: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>, "Pinski, Andrew" <Andrew.Pinski@caviumnetworks.com> Subject: Re: [Patch, MIPS] Add Octeon3 support Date: Fri, 31 Oct 2014 06:49:39 +0000 Message-ID: <1414738195329.46236@caviumnetworks.com> References: <1412659579490.88923@caviumnetworks.com>, <Pine.LNX.4.64.1410071716170.28196@digraph.polyomino.org.uk> <1412750831616.26037@caviumnetworks.com>, <6D39441BF12EF246A7ABCE6654B0235320F2DEBD@LEMAIL01.le.imgtec.org> <1414652377082.43172@caviumnetworks.com>, <FD3DCEAC5B03E9408544A1E416F11242016E75E70E@NA-MBX-04.mgc.mentorg.com> In-Reply-To: <FD3DCEAC5B03E9408544A1E416F11242016E75E70E@NA-MBX-04.mgc.mentorg.com> x-ms-exchange-transport-fromentityheader: Hosted Content-Type: multipart/mixed; boundary="_002_141473819532946236caviumnetworkscom_" MIME-Version: 1.0

diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 28ae552..77455a2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,54 @@ +2014-10-31 Andrew Pinski <apinski@cavium.com> + + * config/mips/mips-cpus.def (octeon3): New cpu. + * config/mips/mips.c (mips_rtx_cost_data): Add octeon3. + (mips_print_operand <case 'T', case 't'>): Fix a bug as the mode + of the comparison no longer matches mode of the operands. + (mips_issue_rate): Handle PROCESSOR_OCTEON3. + * config/mips/mips.h (TARGET_OCTEON): Add Octeon3. + (TARGET_OCTEON2): Likewise. + (TUNE_OCTEON): Add Octeon3. + * config/mips/mips.md (processor): Add octeon3. + * config/mips/octeon.md (octeon_fpu): New automaton and cpu_unit. + (octeon_arith): Add octeon3. + (octeon_condmove): Remove. + (octeon_condmove_o1): New reservation. + (octeon_condmove_o2): New reservation. + (octeon_condmove_o3_int_on_cc): New reservation. + (octeon_load_o2): Add octeon3. + (octeon_cop_o2): Likewise. + (octeon_store): Likewise. + (octeon_brj_o2): Likewise. + (octeon_imul3_o2): Likewise. + (octeon_imul_o2): Likewise. + (octeon_mfhilo_o2): Likewise. + (octeon_imadd_o2): Likewise. + (octeon_idiv_o2_si): Likewise. + (octeon_idiv_o2_di): Likewise. + (octeon_fpu): Add to the automaton. + (octeon_fpu): New cpu unit. + (octeon_condmove_o2): Check for non floating point modes. + (octeon_load_o2): Add prefetchx. + (octeon_cop_o2): Don't check for octeon3. + (octeon3_faddsubcvt): New reservation. + (octeon3_fmul): Likewise. + (octeon3_fmadd): Likewise. + (octeon3_div_sf): Likewise. + (octeon3_div_df): Likewise. + (octeon3_sqrt_sf): Likewise. + (octeon3_sqrt_df): Likewise. + (octeon3_rsqrt_sf): Likewise. + (octeon3_rsqrt_df): Likewise. + (octeon3_fabsnegmov): Likewise. + (octeon_fcond): Likewise. + (octeon_fcondmov): Likewise. + (octeon_fpmtc1): Likewise. + (octeon_fpmfc1): Likewise. + (octeon_fpload): Likewise. + (octeon_fpstore): Likewise. + * config/mips/mips-tables.opt: Regenerate. + * doc/invoke.texi (-march=@var{arch}): Add octeon3. + 2014-10-10 Felix Yang <felix.yang@huawei.com> * config/xtensa/xtensa.h (TARGET_LOOPS): New Macro. diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index d5528d3..e2985b8 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -162,4 +162,5 @@ MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY) +MIPS_CPU ("octeon3", PROCESSOR_OCTEON3, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("xlp", PROCESSOR_XLP, 65, PTF_AVOID_BRANCHLIKELY) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 5791b41..99d2ed8 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -667,5 +667,8 @@ EnumValue Enum(mips_arch_opt_value) String(octeon2) Value(94) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(95) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(95) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(xlp) Value(96) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 3d9db92..3deb6e0 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -975,6 +975,20 @@ static const struct mips_rtx_cost_data 4, /* branch_cost */ 4 /* memory_latency */ }, + /* Octeon III */ + { + COSTS_N_INSNS (6), /* fp_add */ + COSTS_N_INSNS (6), /* fp_mult_sf */ + COSTS_N_INSNS (7), /* fp_mult_df */ + COSTS_N_INSNS (25), /* fp_div_sf */ + COSTS_N_INSNS (48), /* fp_div_df */ + COSTS_N_INSNS (6), /* int_mult_si */ + COSTS_N_INSNS (6), /* int_mult_di */ + COSTS_N_INSNS (18), /* int_div_si */ + COSTS_N_INSNS (35), /* int_div_di */ + 4, /* branch_cost */ + 4 /* memory_latency */ + }, { /* R3900 */ COSTS_N_INSNS (2), /* fp_add */ COSTS_N_INSNS (4), /* fp_mult_sf */ @@ -13172,6 +13186,7 @@ mips_issue_rate (void) case PROCESSOR_R9000: case PROCESSOR_OCTEON: case PROCESSOR_OCTEON2: + case PROCESSOR_OCTEON3: return 2; case PROCESSOR_SB1: diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index c7b998b..726cd48 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -230,8 +230,10 @@ struct mips_cpu_info { #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \ - || mips_arch == PROCESSOR_OCTEON2) -#define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2) + || mips_arch == PROCESSOR_OCTEON2 \ + || mips_arch == PROCESSOR_OCTEON3) +#define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \ + || mips_arch == PROCESSOR_OCTEON3) #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ || mips_arch == PROCESSOR_SB1A) #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) @@ -261,7 +263,8 @@ struct mips_cpu_info { #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \ - || mips_tune == PROCESSOR_OCTEON2) + || mips_tune == PROCESSOR_OCTEON2 \ + || mips_tune == PROCESSOR_OCTEON3) #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ || mips_tune == PROCESSOR_SB1A) #define TUNE_P5600 (mips_tune == PROCESSOR_P5600) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index d47bb78..4b72546 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -41,6 +41,7 @@ m4k octeon octeon2 + octeon3 r3900 r6000 r4000 diff --git a/gcc/config/mips/octeon.md b/gcc/config/mips/octeon.md index 1d6251c..960894f 100644 --- a/gcc/config/mips/octeon.md +++ b/gcc/config/mips/octeon.md @@ -22,41 +22,55 @@ ;; Octeon is a dual-issue processor that can issue all instructions on ;; pipe0 and a subset on pipe1. -(define_automaton "octeon_main, octeon_mult") +(define_automaton "octeon_main, octeon_mult, octeon_fpu") (define_cpu_unit "octeon_pipe0" "octeon_main") (define_cpu_unit "octeon_pipe1" "octeon_main") (define_cpu_unit "octeon_mult" "octeon_mult") +(define_cpu_unit "octeon_fpu" "octeon_fpu") (define_insn_reservation "octeon_arith" 1 - (and (eq_attr "cpu" "octeon,octeon2") + (and (eq_attr "cpu" "octeon,octeon2,octeon3") (eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop")) "octeon_pipe0 | octeon_pipe1") -(define_insn_reservation "octeon_condmove" 2 - (and (eq_attr "cpu" "octeon,octeon2") +(define_insn_reservation "octeon_condmove_o1" 2 + (and (eq_attr "cpu" "octeon") (eq_attr "type" "condmove")) "octeon_pipe0 | octeon_pipe1") +(define_insn_reservation "octeon_condmove_o2" 3 + (and (eq_attr "cpu" "octeon2,octeon3") + (eq_attr "type" "condmove") + (not (eq_attr "mode" "SF, DF"))) + "octeon_pipe0 | octeon_pipe1") + +;; movt/movf can only issue in pipe1 +(define_insn_reservation "octeon_condmove_o3_int_on_cc" 3 + (and (eq_attr "cpu" "octeon2,octeon3") + (eq_attr "type" "condmove") + (not (eq_attr "mode" "SF, DF"))) + "octeon_pipe1") + (define_insn_reservation "octeon_load_o1" 2 (and (eq_attr "cpu" "octeon") (eq_attr "type" "load,prefetch,mtc,mfc")) "octeon_pipe0") (define_insn_reservation "octeon_load_o2" 3 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "load,prefetch")) "octeon_pipe0") ;; ??? memory-related cop0 reads are pipe0 with 3-cycle latency. ;; Front-end-related ones are 1-cycle on pipe1. Assume front-end for now. (define_insn_reservation "octeon_cop_o2" 1 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "mtc,mfc")) "octeon_pipe1") (define_insn_reservation "octeon_store" 1 - (and (eq_attr "cpu" "octeon,octeon2") + (and (eq_attr "cpu" "octeon,octeon2,octeon3") (eq_attr "type" "store")) "octeon_pipe0") @@ -66,7 +80,7 @@ "octeon_pipe0") (define_insn_reservation "octeon_brj_o2" 2 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "branch,jump,call,trap")) "octeon_pipe1") @@ -76,7 +90,7 @@ "(octeon_pipe0 | octeon_pipe1) + octeon_mult") (define_insn_reservation "octeon_imul3_o2" 6 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "imul3,pop,clz")) "octeon_pipe1 + octeon_mult") @@ -86,7 +100,7 @@ "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult") (define_insn_reservation "octeon_imul_o2" 1 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "imul,mthi,mtlo")) "octeon_pipe1 + octeon_mult") @@ -96,7 +110,7 @@ "(octeon_pipe0 | octeon_pipe1) + octeon_mult") (define_insn_reservation "octeon_mfhilo_o2" 6 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "mfhi,mflo")) "octeon_pipe1 + octeon_mult") @@ -106,7 +120,7 @@ "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3") (define_insn_reservation "octeon_imadd_o2" 1 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "imadd")) "octeon_pipe1 + octeon_mult") @@ -116,13 +130,13 @@ "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71") (define_insn_reservation "octeon_idiv_o2_si" 18 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "mode" "SI") (eq_attr "type" "idiv")) "octeon_pipe1 + octeon_mult, octeon_mult*17") (define_insn_reservation "octeon_idiv_o2_di" 35 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "mode" "DI") (eq_attr "type" "idiv")) "octeon_pipe1 + octeon_mult, octeon_mult*34") @@ -131,6 +145,95 @@ ;; patterns. (define_insn_reservation "octeon_unknown" 1 - (and (eq_attr "cpu" "octeon,octeon2") + (and (eq_attr "cpu" "octeon,octeon2,octeon3") (eq_attr "type" "unknown,multi,atomic,syncloop")) "octeon_pipe0 + octeon_pipe1") + +;; Octeon3 FPU + +(define_insn_reservation "octeon3_faddsubcvt" 4 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fadd, fcvt")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon3_fmul" 5 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fmul")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon3_fmadd" 9 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fmadd")) + "octeon_pipe1 + octeon_fpu, octeon_fpu") + +(define_insn_reservation "octeon3_div_sf" 12 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fdiv, frdiv") + (eq_attr "mode" "SF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*8") + +(define_insn_reservation "octeon3_div_df" 22 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fdiv, frdiv") + (eq_attr "mode" "SF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*18") + +(define_insn_reservation "octeon3_sqrt_sf" 16 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fsqrt") + (eq_attr "mode" "SF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*12") + +(define_insn_reservation "octeon3_sqrt_df" 30 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fsqrt") + (eq_attr "mode" "DF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*26") + +(define_insn_reservation "octeon3_rsqrt_sf" 27 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "frsqrt") + (eq_attr "mode" "SF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*23") + +(define_insn_reservation "octeon3_rsqrt_df" 51 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "frsqrt") + (eq_attr "mode" "DF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*47") + +(define_insn_reservation "octeon3_fabsnegmov" 2 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fabs, fneg, fmove")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon_fcond" 1 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fcmp")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon_fcondmov" 2 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "condmove") + (eq_attr "mode" "SF,DF")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon_fpmtc1" 2 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "mtc")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon_fpmfc1" 6 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "mtc")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon_fpload" 3 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fpload,fpidxload")) + "octeon_pipe0 + octeon_fpu") + +(define_insn_reservation "octeon_fpstore" 3 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fpstore,fpidxstore")) + "octeon_pipe0 + octeon_pipe1") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 792f25b..b75ebc7 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -17531,7 +17531,7 @@ The processor names are: @samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, -@samp{octeon}, @samp{octeon+}, @samp{octeon2}, +@samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{octeon3}, @samp{orion}, @samp{p5600}, @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400}, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3aa9b6b..f3ebee5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2014-10-31 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> + + * gcc.target/mips/octeon3-pipe-1.c: New test. + 2014-10-30 Marek Polacek <polacek@redhat.com> * gcc.dg/diag-aka-1.c: New test. diff --git a/gcc/testsuite/gcc.target/mips/octeon3-pipe-1.c b/gcc/testsuite/gcc.target/mips/octeon3-pipe-1.c new file mode 100644 index 0000000..3b83266 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/octeon3-pipe-1.c @@ -0,0 +1,12 @@ +/* Check that we use the octeon3 pipeline description. */ +/* { dg-do compile } */ +/* { dg-options "-fschedule-insns2 -fdump-rtl-sched2 -march=octeon3" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 int f (int a, int b) +{ + return a / b; +} + +/* { dg-final { scan-rtl-dump "octeon_mult\\*17" "sched2" } } */ +/* { dg-final { cleanup-rtl-dump "sched2" } } */

[MIPS] Add Octeon3 support

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