[1/6] sata_mv: increase PIO IORDY timeout

Submitted by Saeed Bishara on Dec. 6, 2009, 4:26 p.m.

Details

Message ID 1260116782-31714-1-git-send-email-saeed@marvell.com
State Not Applicable
Delegated to: David Miller
Headers show

Commit Message

Saeed Bishara Dec. 6, 2009, 4:26 p.m.
The old value (0xbc) in cycles of the IORDY timeout is suitable for
devices with core clock of 166 MHz, but some SoC controllers have
faster core clocks. The new value will make the IORDY timeout large
enough also for all SoC devices.

Signed-off-by: Saeed Bishara <saeed@marvell.com>
---
 drivers/ata/sata_mv.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Comments

Jeff Garzik Dec. 17, 2009, 6:03 a.m.
On 12/06/2009 11:26 AM, Saeed Bishara wrote:
> The old value (0xbc) in cycles of the IORDY timeout is suitable for
> devices with core clock of 166 MHz, but some SoC controllers have
> faster core clocks. The new value will make the IORDY timeout large
> enough also for all SoC devices.
>
> Signed-off-by: Saeed Bishara<saeed@marvell.com>
> ---
>   drivers/ata/sata_mv.c |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)

applied 1-4


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Patch hide | download patch | download mbox

diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 6f5093b..312c3e0 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -3393,7 +3393,7 @@  static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
 	ZERO(0x024);		/* respq outp */
 	ZERO(0x020);		/* respq inp */
 	ZERO(0x02c);		/* test control */
-	writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
+	writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
 }
 
 #undef ZERO