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[U-Boot,6/7,v2] spi: altera: Add short note about EPCS/EPCQx1

Message ID 1414007764-24094-6-git-send-email-marex@denx.de
State Accepted
Delegated to: Jagannadha Sutradharudu Teki
Headers show

Commit Message

Marek Vasut Oct. 22, 2014, 7:56 p.m. UTC 
Add short documentation-alike note on how to use the Altera SPI
driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V
into doc/SPI/README.altera_spi

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
---
 doc/SPI/README.altera_spi | 6 ++++++
 1 files changed, 6 insertions(+)
 create mode 100644 doc/SPI/README.altera_spi

V2: Move the documentation into doc/SPI/README.altera_spi
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Patch

diff --git a/doc/SPI/README.altera_spi b/doc/SPI/README.altera_spi
new file mode 100644
index 0000000..b07449f
--- /dev/null
+++ b/doc/SPI/README.altera_spi
@@ -0,0 +1,6 @@ 
+SoCFPGA EPCS/EPCQx1 mini howto:
+- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild
+- The controller base address is the "Base" in QSys + 0x400
+- Set MSEL[4:0]=10010 (AS Standard)
+- Load the bitstream into FPGA, enable bridges
+- Only then will the driver work