@@ -33188,6 +33188,151 @@ ix86_init_mmx_sse_builtins (void)
VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
IX86_BUILTIN_SCATTERDIV8DI);
+ /* AVX512VL */
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2df",
+ V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
+ IX86_BUILTIN_GATHER3SIV2DF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4df",
+ V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
+ IX86_BUILTIN_GATHER3SIV4DF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2df",
+ V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
+ IX86_BUILTIN_GATHER3DIV2DF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4df",
+ V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
+ IX86_BUILTIN_GATHER3DIV4DF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4sf",
+ V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
+ IX86_BUILTIN_GATHER3SIV4SF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8sf",
+ V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
+ IX86_BUILTIN_GATHER3SIV8SF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4sf",
+ V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
+ IX86_BUILTIN_GATHER3DIV4SF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8sf",
+ V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
+ IX86_BUILTIN_GATHER3DIV8SF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2di",
+ V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
+ IX86_BUILTIN_GATHER3SIV2DI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4di",
+ V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
+ IX86_BUILTIN_GATHER3SIV4DI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2di",
+ V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
+ IX86_BUILTIN_GATHER3DIV2DI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4di",
+ V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
+ IX86_BUILTIN_GATHER3DIV4DI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4si",
+ V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
+ IX86_BUILTIN_GATHER3SIV4SI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8si",
+ V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
+ IX86_BUILTIN_GATHER3SIV8SI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4si",
+ V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
+ IX86_BUILTIN_GATHER3DIV4SI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8si",
+ V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
+ IX86_BUILTIN_GATHER3DIV8SI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altsiv4df ",
+ V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
+ IX86_BUILTIN_GATHER3ALTSIV4DF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altdiv8sf ",
+ V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
+ IX86_BUILTIN_GATHER3ALTDIV8SF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altsiv4di ",
+ V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
+ IX86_BUILTIN_GATHER3ALTSIV4DI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altdiv8si ",
+ V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
+ IX86_BUILTIN_GATHER3ALTDIV8SI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv8sf",
+ VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
+ IX86_BUILTIN_SCATTERSIV8SF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv4sf",
+ VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
+ IX86_BUILTIN_SCATTERSIV4SF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv4df",
+ VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
+ IX86_BUILTIN_SCATTERSIV4DF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv2df",
+ VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
+ IX86_BUILTIN_SCATTERSIV2DF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv8sf",
+ VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
+ IX86_BUILTIN_SCATTERDIV8SF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv4sf",
+ VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
+ IX86_BUILTIN_SCATTERDIV4SF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv4df",
+ VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
+ IX86_BUILTIN_SCATTERDIV4DF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv2df",
+ VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
+ IX86_BUILTIN_SCATTERDIV2DF);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv8si",
+ VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
+ IX86_BUILTIN_SCATTERSIV8SI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv4si",
+ VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
+ IX86_BUILTIN_SCATTERSIV4SI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv4di",
+ VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
+ IX86_BUILTIN_SCATTERSIV4DI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv2di",
+ VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
+ IX86_BUILTIN_SCATTERSIV2DI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv8si",
+ VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
+ IX86_BUILTIN_SCATTERDIV8SI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv4si",
+ VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
+ IX86_BUILTIN_SCATTERDIV4SI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv4di",
+ VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
+ IX86_BUILTIN_SCATTERDIV4DI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scatterdiv2di",
+ VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
+ IX86_BUILTIN_SCATTERDIV2DI);
+
/* AVX512PF */
def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfdpd",
VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,